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    Method of manufacturing complementary metal oxide semiconductor device
    1.
    发明授权
    Method of manufacturing complementary metal oxide semiconductor device 有权
    互补金属氧化物半导体器件的制造方法

    公开(公告)号：US08278166B2

    公开(公告)日：2012-10-02

    申请号：US12837519

    申请日：2010-07-16

    申请人： Chun-Chia Chen ,  Ying-Hung Chou ,  Zen-Jay Tsai ,  Shih-Chieh Hsu ,  Yi-Chung Sheng ,  Chi-Horn Pai

    发明人： Chun-Chia Chen ,  Ying-Hung Chou ,  Zen-Jay Tsai ,  Shih-Chieh Hsu ,  Yi-Chung Sheng ,  Chi-Horn Pai

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/7848

    摘要： A method of manufacturing a CMOS device includes providing a substrate having a first region and a second region; forming a first gate structure and a second gate structure, each of the gate structures comprising a sacrificial layer and a hard mask layer; forming a patterned first protecting layer covering the first region and a first spacer on sidewalls of the second gate structure; performing an etching process to form first recesses in the substrate; performing a SEG process to form epitaxial silicon layers in each first recess; forming a patterned second protecting layer covering the second region; and performing a dry etching process with the patterned second protecting layer serving as an etching mask to etch back the patterned first protecting layer to form a second spacer on sidewalls of the first gate structure and to thin down the hard mask layer on the first gate structure.

    摘要翻译： 制造CMOS器件的方法包括提供具有第一区域和第二区域的衬底; 形成第一栅极结构和第二栅极结构，每个栅极结构包括牺牲层和硬掩模层; 形成覆盖所述第一区域的图案化的第一保护层和在所述第二栅极结构的侧壁上的第一间隔物; 进行蚀刻工艺以在基板中形成第一凹部; 执行SEG工艺以在每个第一凹部中形成外延硅层; 形成覆盖所述第二区域的图案化的第二保护层; 以及利用所述图案化的第二保护层作为蚀刻掩模进行干蚀刻工艺，以蚀刻所述图案化的第一保护层，以在所述第一栅极结构的侧壁上形成第二间隔物，并且使所述第一栅极结构上的所述硬掩模层变薄 。

    METHOD OF MANUFACTURING COMPLEMENTARY METAL OXIDE SEMICONDUCTOR DEVICE
    2.
    发明申请
    METHOD OF MANUFACTURING COMPLEMENTARY METAL OXIDE SEMICONDUCTOR DEVICE 有权
    制备补充金属氧化物半导体器件的方法

    公开(公告)号：US20120012938A1

    公开(公告)日：2012-01-19

    申请号：US12837519

    申请日：2010-07-16

    申请人： Chun-Chia Chen ,  Ying-Hung Chou ,  Zen-Jay Tsai ,  Shih-Chieh Hsu ,  Yi-Chung Sheng ,  Chi-Horn Pai

    发明人： Chun-Chia Chen ,  Ying-Hung Chou ,  Zen-Jay Tsai ,  Shih-Chieh Hsu ,  Yi-Chung Sheng ,  Chi-Horn Pai

    IPC分类号： H01L27/092 ,  H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/7848

    摘要： A method of manufacturing a CMOS device includes providing a substrate having a first region and a second region; forming a first gate structure and a second gate structure, each of the gate structures comprising a sacrificial layer and a hard mask layer; forming a patterned first protecting layer covering the first region and a first spacer on sidewalls of the second gate structure; performing an etching process to form first recesses in the substrate; performing a SEG process to form epitaxial silicon layers in each first recess; forming a patterned second protecting layer covering the second region; and performing a dry etching process with the patterned second protecting layer serving as an etching mask to etch back the patterned first protecting layer to form a second spacer on sidewalls of the first gate structure and to thin down the hard mask layer on the first gate structure.

    摘要翻译： 制造CMOS器件的方法包括提供具有第一区域和第二区域的衬底; 形成第一栅极结构和第二栅极结构，每个栅极结构包括牺牲层和硬掩模层; 形成覆盖所述第一区域的图案化的第一保护层和在所述第二栅极结构的侧壁上的第一间隔物; 进行蚀刻工艺以在基板中形成第一凹部; 执行SEG工艺以在每个第一凹槽中形成外延硅层; 形成覆盖所述第二区域的图案化的第二保护层; 以及利用所述图案化的第二保护层作为蚀刻掩模进行干蚀刻工艺，以蚀刻所述图案化的第一保护层，以在所述第一栅极结构的侧壁上形成第二间隔物，并且使所述第一栅极结构上的所述硬掩模层变薄 。

    Method for fabricating a semiconductor device
    3.
    发明授权
    Method for fabricating a semiconductor device 有权
    半导体器件的制造方法

    公开(公告)号：US08207043B2

    公开(公告)日：2012-06-26

    申请号：US12568657

    申请日：2009-09-28

    申请人： Huang-Yi Lin ,  Jiun-Hung Shen ,  Chi-Horn Pai ,  Yi-Chung Sheng ,  Shih-Chieh Hsu

    发明人： Huang-Yi Lin ,  Jiun-Hung Shen ,  Chi-Horn Pai ,  Yi-Chung Sheng ,  Shih-Chieh Hsu

    IPC分类号： H01L21/336

    CPC分类号： H01L29/78 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/268 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7847

    摘要： A method for making a semiconductor MOS device is provided. A gate structure is formed on a substrate. A source and a drain are formed in the substrate on both sides of the gate structure. The substrate is then subjected to a pre-amorphization implant (PAI) process. A transitional stress layer is then formed on the substrate. Thereafter, a laser anneal with a first temperature is performed. After the laser anneal, a rapid thermal process is performed with a second temperature that is lower than the first temperature. Subsequently, the transitional stress layer is removed.

    摘要翻译： 提供了制造半导体MOS器件的方法。 在基板上形成栅极结构。 源极和漏极形成在栅极结构两侧的衬底中。 然后将基材进行预非晶化植入（PAI）工艺。 然后在衬底上形成过渡应力层。 此后，进行具有第一温度的激光退火。 在激光退火之后，以低于第一温度的第二温度进行快速热处理。 随后，去除过渡应力层。

    METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE
    5.
    发明申请
    METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE 有权
    制造半导体器件的方法

    公开(公告)号：US20110076823A1

    公开(公告)日：2011-03-31

    申请号：US12568657

    申请日：2009-09-28

    申请人： Huang-Yi Lin ,  Jiun-Hung Shen ,  Chi-Horn Pai ,  Yi-Chung Sheng ,  Shih-Chieh Hsu

    发明人： Huang-Yi Lin ,  Jiun-Hung Shen ,  Chi-Horn Pai ,  Yi-Chung Sheng ,  Shih-Chieh Hsu

    IPC分类号： H01L21/336

    CPC分类号： H01L29/78 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/268 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7847

    摘要： A method for making a semiconductor MOS device is provided. A gate structure is formed on a substrate. A source and a drain are formed in the substrate on both sides of the gate structure. The substrate is then subjected to a pre-amorphization implant (PAI) process. A transitional stress layer is then formed on the substrate. Thereafter, a laser anneal with a first temperature is performed. After the laser anneal, a rapid thermal process is performed with a second temperature that is lower than the first temperature. Subsequently, the transitional stress layer is removed.

    摘要翻译： 提供了制造半导体MOS器件的方法。 在基板上形成栅极结构。 源极和漏极形成在栅极结构两侧的衬底中。 然后将基材进行预非晶化植入（PAI）工艺。 然后在衬底上形成过渡应力层。 此后，进行具有第一温度的激光退火。 在激光退火之后，以低于第一温度的第二温度进行快速热处理。 随后，去除过渡应力层。

    Semiconductor circuit structure
    6.
    发明授权
    Semiconductor circuit structure 有权
    半导体电路结构

    公开(公告)号：US08624398B2

    公开(公告)日：2014-01-07

    申请号：US12547521

    申请日：2009-08-26

    申请人： Chia-Chen Sun ,  Shih-Chieh Hsu ,  Yi-Chung Sheng ,  Sheng-Yuan Hsueh ,  Yao-Chang Wang

    发明人： Chia-Chen Sun ,  Shih-Chieh Hsu ,  Yi-Chung Sheng ,  Sheng-Yuan Hsueh ,  Yao-Chang Wang

    IPC分类号： H01L23/52

    CPC分类号： G06F17/5081 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor circuit structure includes a substrate and an interconnect structure. The interconnect structure is disposed on the substrate and includes a plurality of circuit patterns and at least one closed loop pattern. The closed loop pattern is in a same layer with the circuit patterns, surrounds between the circuit patterns and is insulated from the circuit patterns. The closed loop pattern can protect the circuit patterns from being damaged by stresses, for improving a mechanical strength of the semiconductor circuit structure.

    摘要翻译： 半导体电路结构包括基板和互连结构。 互连结构设置在衬底上并且包括多个电路图案和至少一个闭环图案。 闭环图案与电路图案处于相同的层中，在电路图案之间包围并与电路图案绝缘。 闭环图案可以保护电路图案不被应力损坏，以改善半导体电路结构的机械强度。

    Method of fabricating semiconductor device for preventing polysilicon line being damaged during removal of photoresist
    7.
    发明授权
    Method of fabricating semiconductor device for preventing polysilicon line being damaged during removal of photoresist 有权

    公开(公告)号：US06544849B2

    公开(公告)日：2003-04-08

    申请号：US09852254

    申请日：2001-05-09

    申请人： Shih-Chieh Hsu ,  Yi-Chung Sheng ,  Chang-Chi Huang ,  Sheng-Hao Lin ,  Cheng-Tung Huang

    发明人： Shih-Chieh Hsu ,  Yi-Chung Sheng ,  Chang-Chi Huang ,  Sheng-Hao Lin ,  Cheng-Tung Huang

    IPC分类号： H01L218234

    CPC分类号： H01L21/823425

    摘要： A method of fabricating the semiconductor device for preventing polysilicon line from being damaged during removal of a photoresist layer. The method begins by forming polysilicon lines on a core device region and an electrostatic discharge protection device region of a substrate. A plurality of offset spacers is formed on sidewalls of the polysilicon lines. After the offset spacers are formed, a photoresist layer is formed over the substrate to cover the core device region, while exposing the electrostatic discharge protection device region. With the photoresist layer serving as a mask, a punch-through ion implantation is performed on the electrostatic discharge protection device region before the photoresist layer is removed. Next, a plurality of lightly doped source/drain regions is formed in the core device region. A spacer is further formed on the edge of the offset spacer, followed by forming source/drain regions in the core device region and the electrostatic discharge protection device. Since the offset spacers are formed on the sidewalls of the polysilicon lines before the photoresist layer is removed, the offset spacers can protect the polysilicon lines from being broken.

    Semiconductor Circuit Structure and Layout Method thereof
    8.
    发明申请
    Semiconductor Circuit Structure and Layout Method thereof 有权
    半导体电路结构及其布局方法

    公开(公告)号：US20110049722A1

    公开(公告)日：2011-03-03

    申请号：US12547521

    申请日：2009-08-26

    申请人： Chia-Chen Sun ,  Shih-Chieh Hsu ,  Yi-Chung Sheng ,  Sheng-Yuan Hsueh ,  Yao-Chang Wang

    发明人： Chia-Chen Sun ,  Shih-Chieh Hsu ,  Yi-Chung Sheng ,  Sheng-Yuan Hsueh ,  Yao-Chang Wang

    IPC分类号： H01L23/52 ,  G06F17/50

    CPC分类号： G06F17/5081 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor circuit structure includes a substrate and an interconnect structure. The interconnect structure is disposed on the substrate and includes a plurality of circuit patterns and at least one closed loop pattern. The closed loop pattern is in a same layer with the circuit patterns, surrounds between the circuit patterns and is insulated from the circuit patterns. The closed loop pattern can protect the circuit patterns from being damaged by stresses, for improving a mechanical strength of the semiconductor circuit structure.

    摘要翻译： 半导体电路结构包括基板和互连结构。 互连结构设置在衬底上并且包括多个电路图案和至少一个闭环图案。 闭环图案与电路图案处于相同的层中，在电路图案之间包围并与电路图案绝缘。 闭环图案可以保护电路图案不被应力损坏，以改善半导体电路结构的机械强度。

    Method of forming a CMOS transistor
    9.
    发明授权
    Method of forming a CMOS transistor 有权
    形成CMOS晶体管的方法

    公开(公告)号：US6127212A

    公开(公告)日：2000-10-03

    申请号：US488811

    申请日：2000-01-21

    申请人： Chin-Lan Chen ,  Cheng-Tung Huang ,  Shih-Chieh Hsu ,  Yi-Chung Sheng

    发明人： Chin-Lan Chen ,  Cheng-Tung Huang ,  Shih-Chieh Hsu ,  Yi-Chung Sheng

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823864

    摘要： The present invention provides a method for forming a CMOS transistor on a semiconductor wafer. The semiconductor wafer comprises a substrate, a first gate positioned on the substrate being used to form a PMOS transistor of the CMOS transistor, and a second gate positioned on the substrate being used to form an NMOS transistor of the CMOS transistor. First spacers are formed on both lateral surfaces of the first gate and of the second gate. A first ion implantation process is performed to form a pair of first doped regions in the substrate, oppositely adjacent to the first gate, the pair of first doped regions to serve as heavy doped drain (HDD) of the PMOS transistor. Then the thickness of the first spacers is reduced. A second ion implantation process is performed to form a pair of second doped regions in the substrate, oppositely adjacent to the second gate, the pair of second doped regions to serve as the HDD of the NMOS transistor. Second spacers are then formed covering each first spacer. Finally, sources/drains for the PMOS transistor and the NMOS transistor are formed in the substrate, oppositely adjacent to the first gate and the second gate.

    摘要翻译： 本发明提供一种在半导体晶片上形成CMOS晶体管的方法。 半导体晶片包括衬底，位于衬底上的第一栅极用于形成CMOS晶体管的PMOS晶体管，以及位于衬底上的第二栅极，用于形成CMOS晶体管的NMOS晶体管。 第一间隔件形成在第一栅极和第二栅极的两个侧表面上。 执行第一离子注入工艺以在衬底中形成一对与第一栅极相对的第一掺杂区域，该对第一掺杂区域用作PMOS晶体管的重掺杂漏极（HDD）。 然后减小第一间隔物的厚度。 执行第二离子注入工艺以在衬底中形成与第二栅极相对的一对第二掺杂区域，该对第二掺杂区域用作NMOS晶体管的HDD。 然后形成覆盖每个第一间隔物的第二间隔物。 最后，PMOS晶体管和NMOS晶体管的源极/漏极形成在与第一栅极和第二栅极相对的衬底中。