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    Display pixel having oxide thin-film transistor (TFT) with reduced loading
    1.
    发明授权
    Display pixel having oxide thin-film transistor (TFT) with reduced loading 有权
    具有减小负载的具有氧化物薄膜晶体管（TFT）的显示像素

    公开(公告)号：US08988624B2

    公开(公告)日：2015-03-24

    申请号：US13243317

    申请日：2011-09-23

    申请人： Chun-Yao Huang ,  Young Bae Park ,  Shih Chang Chang

    发明人： Chun-Yao Huang ,  Young Bae Park ,  Shih Chang Chang

    IPC分类号： G02F1/136 ,  G02F1/1362 ,  H01L29/786 ,  H01L27/12

    CPC分类号： G02F1/1362 ,  G02F1/136286 ,  G02F2001/13606 ,  G02F2201/40 ,  H01L27/1225 ,  H01L29/7869

    摘要： Disclosed embodiments relate to a thin-film transistor (TFT) for use in a display device. The display device may include a liquid crystal display (LCD) panel having multiple pixels arranged in rows and column, with each row corresponding to a gate line and each column corresponding to a source line. Each of the pixels includes a pixel electrode and a TFT. The TFT may include a metal oxide semiconductor channel between a source and drain. For each TFT, holes may be formed in the gate line in a region beneath the source and/or the drain. The holes may be formed such that the source and drain only partially overlap the holes. The presence of the holes reduces the area of the gate line, which may reduce parasitic capacitance and improve loading. This may provide improved panel performance, which may reduce the appearance of certain visual artifacts.

    摘要翻译： 公开的实施例涉及用于显示装置的薄膜晶体管（TFT）。 显示装置可以包括具有排列成行和列的多个像素的液晶显示器（LCD）面板，每行对应于栅极线，每列对应于源极线。 每个像素包括像素电极和TFT。 TFT可以在源极和漏极之间包括金属氧化物半导体沟道。 对于每个TFT，可以在源极和/或漏极下方的区域中的栅极线中形成空穴。 孔可以形成为使得源极和漏极仅部分地与孔重叠。 孔的存在减小了栅极线的面积，这可能减少寄生电容并改善负载。 这可以提供改进的面板性能，这可以减少某些视觉伪影的外观。

    DISPLAY PIXEL HAVING OXIDE THIN-FILM TRANSISTOR (TFT) WITH REDUCED LOADING
    2.
    发明申请
    DISPLAY PIXEL HAVING OXIDE THIN-FILM TRANSISTOR (TFT) WITH REDUCED LOADING 有权
    具有减少负载的氧化物薄膜晶体管（TFT）的显示像素

    公开(公告)号：US20120327321A1

    公开(公告)日：2012-12-27

    申请号：US13243317

    申请日：2011-09-23

    申请人： Chun-Yao Huang ,  Young Bae Park ,  Shih Chang Chang

    发明人： Chun-Yao Huang ,  Young Bae Park ,  Shih Chang Chang

    IPC分类号： G02F1/136 ,  H01L21/336

    CPC分类号： G02F1/1362 ,  G02F1/136286 ,  G02F2001/13606 ,  G02F2201/40 ,  H01L27/1225 ,  H01L29/7869

    摘要： Disclosed embodiments relate to a thin-film transistor (TFT) for use in a display device. The display device may include a liquid crystal display (LCD) panel having multiple pixels arranged in rows and column, with each row corresponding to a gate line and each column corresponding to a source line. Each of the pixels includes a pixel electrode and a TFT. The TFT may include a metal oxide semiconductor channel between a source and drain. For each TFT, holes may be formed in the gate line in a region beneath the source and/or the drain. The holes may be formed such that the source and drain only partially overlap the holes. The presence of the holes reduces the area of the gate line, which may reduce parasitic capacitance and improve loading. This may provide improved panel performance, which may reduce the appearance of certain visual artifacts.

    摘要翻译： 公开的实施例涉及用于显示装置的薄膜晶体管（TFT）。 显示装置可以包括具有排列成行和列的多个像素的液晶显示器（LCD）面板，每行对应于栅极线，每列对应于源极线。 每个像素包括像素电极和TFT。 TFT可以在源极和漏极之间包括金属氧化物半导体沟道。 对于每个TFT，可以在源极和/或漏极下方的区域中的栅极线中形成空穴。 孔可以形成为使得源极和漏极仅部分地与孔重叠。 孔的存在减小了栅极线的面积，这可能减少寄生电容并改善负载。 这可以提供改进的面板性能，这可以减少某些视觉伪影的外观。

    TFT mask reduction
    3.
    发明授权
    TFT mask reduction 有权
    TFT面膜减少

    公开(公告)号：US08801948B2

    公开(公告)日：2014-08-12

    申请号：US13610712

    申请日：2012-09-11

    申请人： Ming-Chin Hung ,  Youngbae Park ,  Chun-Yao Huang ,  Shih Chang Chang ,  John Z. Zhong

    发明人： Ming-Chin Hung ,  Youngbae Park ,  Chun-Yao Huang ,  Shih Chang Chang ,  John Z. Zhong

    IPC分类号： B44C1/22 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00

    CPC分类号： H01L21/308 ,  H01L21/0274 ,  H01L21/31144 ,  H01L21/32139 ,  H01L27/1288

    摘要： Embodiments of the present disclosure relate to display devices and methods for manufacturing display devices. Specifically, embodiments of the present disclosure employ a halftone photoresist layer useful for reducing a number of masks needed to manufacture TFT backplane (e.g., thin-film transistors (TFTs) with fringe-field shifting). The halftone photoresist layer defines two areas, one defining an etching area for a first layer (e.g., a common voltage layer) and the other defining an etching area for a second layer (e.g., an organic passivation layer).

    摘要翻译： 本公开的实施例涉及用于制造显示设备的显示设备和方法。 具体地，本公开的实施例采用半色调光致抗蚀剂层，其可用于减少制造TFT背板所需的掩模数量（例如，具有边缘场移位的薄膜晶体管（TFT））。 半色调光致抗蚀剂层限定两个区域，一个限定第一层（例如，公共电压层）的蚀刻区域，另一个限定第二层（例如，有机钝化层）的蚀刻区域。

    TFT Mask Reduction
    4.
    发明申请
    TFT Mask Reduction 有权
    TFT面膜减少

    公开(公告)号：US20140004704A1

    公开(公告)日：2014-01-02

    申请号：US13610712

    申请日：2012-09-11

    申请人： Ming-Chin Hung ,  Youngbae Park ,  Chun-Yao Huang ,  Shih Chang Chang ,  John Z. Zhong

    发明人： Ming-Chin Hung ,  Youngbae Park ,  Chun-Yao Huang ,  Shih Chang Chang ,  John Z. Zhong

    IPC分类号： H01L21/308

    CPC分类号： H01L21/308 ,  H01L21/0274 ,  H01L21/31144 ,  H01L21/32139 ,  H01L27/1288

    摘要： Embodiments of the present disclosure relate to display devices and methods for manufacturing display devices. Specifically, embodiments of the present disclosure employ a halftone photoresist layer useful for reducing a number of masks needed to manufacture TFT backplane (e.g., thin-film transistors (TFTs) with fringe-field shifting). The halftone photoresist layer defines two areas, one defining an etching area for a first layer (e.g., a common voltage layer) and the other defining an etching area for a second layer (e.g., an organic passivation layer).

    摘要翻译： 本公开的实施例涉及用于制造显示设备的显示设备和方法。 具体地，本公开的实施例采用半色调光致抗蚀剂层，其可用于减少制造TFT背板所需的掩模数量（例如，具有边缘场移位的薄膜晶体管（TFT））。 半色调光致抗蚀剂层限定两个区域，一个限定第一层（例如，公共电压层）的蚀刻区域，另一个限定第二层（例如，有机钝化层）的蚀刻区域。

    Two Doping Regions in Lightly Doped Drain for Thin Film Transistors and Associated Doping Processes
    7.
    发明申请
    Two Doping Regions in Lightly Doped Drain for Thin Film Transistors and Associated Doping Processes 有权
    用于薄膜晶体管和相关掺杂过程的轻掺杂漏极中的两个掺杂区域

    公开(公告)号：US20140061656A1

    公开(公告)日：2014-03-06

    申请号：US13601535

    申请日：2012-08-31

    申请人： Cheng-Ho Yu ,  Young Bae Park ,  Shih Chang Chang

    发明人： Cheng-Ho Yu ,  Young Bae Park ,  Shih Chang Chang

    IPC分类号： H01L27/15 ,  H01L33/08

    CPC分类号： H01L29/78621 ,  H01L27/1288 ,  H01L29/78645 ,  H01L29/78696

    摘要： A method is provided for fabricating thin-film transistors (TFTs) for an LCD having an array of pixels. The method includes depositing a first photoresist layer over a portion of a TFT stack that includes a conductive gate layer, and a semiconductor layer. The method also includes doping the exposed semiconductor layer with a first doping dose. The method further includes etching a portion of the conductive gate layer to expose a portion of the semiconductor layer, and doping the exposed portion of the semiconductor layer with a second doping dose. The method also includes depositing a second photoresist layer over a first portion of the doped semiconductor layer in an active area of the pixels to expose a second portion of the doped semiconductor layer in an area surrounding the active area, and doping the second portion of the doped semiconductor layer with a third doping dose.

    摘要翻译： 提供了一种制造用于具有像素阵列的LCD的薄膜晶体管（TFT）的方法。 该方法包括在包括导电栅极层的TFT堆叠的一部分上沉积第一光致抗蚀剂层和半导体层。 该方法还包括以第一掺杂剂量掺杂暴露的半导体层。 该方法还包括蚀刻导电栅极层的一部分以暴露半导体层的一部分，并以第二掺杂剂量掺杂半导体层的暴露部分。 该方法还包括在像素的有源区域中在掺杂半导体层的第一部分上沉积第二光致抗蚀剂层，以在有源区域周围的区域中暴露掺杂半导体层的第二部分，以及掺杂半导体层的第二部分 掺杂半导体层具有第三掺杂剂量。

    DATA LINE-TO-PIXEL DECOUPLING
    10.
    发明申请
    DATA LINE-TO-PIXEL DECOUPLING 有权
    数据线到像素解密

    公开(公告)号：US20130076600A1

    公开(公告)日：2013-03-28

    申请号：US13245635

    申请日：2011-09-26

    申请人： Young Bae Park ,  Cheng Chen ,  Shih Chang Chang ,  Zhibing Ge ,  John Z. Zhong

    发明人： Young Bae Park ,  Cheng Chen ,  Shih Chang Chang ,  Zhibing Ge ,  John Z. Zhong

    IPC分类号： G09G3/20 ,  C23F1/08 ,  H01J9/00

    CPC分类号： G02F1/136286 ,  G02F2001/13606 ,  G09G2300/0426 ,  G09G2300/043

    摘要： Embodiments of the present disclosure relate to display devices and electronic devices incorporating a data line distribution segment between neighboring pixel electrodes. Specifically, embodiments of the present disclosure employ a uniformly distributed data line distribution segment coupled to a data line so as to cause a substantially uniform data line-to-pixel electrode capacitance with the neighboring pixel electrodes even when the data line is disposed closer to one of the neighboring pixel electrodes than the other.

    摘要翻译： 本公开的实施例涉及在相邻像素电极之间并入数据线分布段的显示装置和电子装置。 具体地，本公开的实施例采用均匀分布的数据线分布段，其耦合到数据线，以便即使当数据线设置得更接近于一个时，也会使得与相邻像素电极的数据线到像素电极电容基本上均匀 的相邻像素电极。