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公开(公告)号：US06496037B1
公开(公告)日：2002-12-17
申请号：US09588202
申请日：2000-06-06
IPC分类号： H03K190175
CPC分类号： H03K19/0005
摘要： An automatic driver adjuster and methods using the same are provided that modify off-chip drivers based on load characteristics. The preferred embodiments are preferably automatic and require little or no human intervention. Preferred embodiments of the current invention analyze and determine the impedance of a node and adjust a number of output drivers in response to the impedance of the node, or analyze a resultant waveform of the node, caused by an input waveform, and adjust a number of output drivers in response to the resultant waveform of the node.
摘要翻译： 提供了一种自动驱动器调节器及其使用方法，其基于负载特性修改片外驱动器。 优选的实施方案优选是自动的，并且需要很少的或不需要人为干预。 本发明的优选实施例分析和确定节点的阻抗并且响应于节点的阻抗调整输出驱动器的数量，或者分析由输入波形引起的节点的合成波形，并且调整多个 输出驱动器响应于该结点的合成波形。
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2.发明授权公开(公告)号：US06879638B1
公开(公告)日：2005-04-12
申请号：US09473935
申请日：1999-12-28
CPC分类号： H04L25/4906 , H04L25/4902
摘要： A method and system for providing communication between electronic devices that uses the phase of data transmitted between the devices to indicate logical one and zero values. The method and system has the added benefit of relieving the traditional limitations of voltage communication restraints between devices having differing core voltages (i.e. Differing generations).
摘要翻译： 一种用于在电子设备之间提供通信的方法和系统，其使用在设备之间传输的数据的相位来指示逻辑1和零值。 该方法和系统具有减轻在具有不同核心电压的器件（即不同代）之间的电压通信约束的传统限制的附加益处。
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3.发明授权公开(公告)号：US06281731B1
公开(公告)日：2001-08-28
申请号：US09428639
申请日：1999-10-27
IPC分类号： H03K3297
CPC分类号： H03K3/3565 , H03K3/02337
摘要： A differential receiver has a switching point accurately set according to a reference voltage, which switching point is dynamically modified, that is, dc hysteresis is provided, by a circuit internal to the differential receiver. Positioning of the resultant hysteresis characteristic about the reference signal is adjusted by establishing a backgate voltage differential between an input transistor and a reference transistor of the differential receiver. A switching circuit is also provided for controlling switching of a hysteresis circuit at the reference signal plus or minus a desired offset. The switching circuit is gated by an output signal of the input transistor.
摘要翻译： 差分接收器具有根据参考电压精确设置的开关点，通过差分接收器内部的电路动态地修改切换点，即提供直流滞后。 通过在差分接收器的输入晶体管和参考晶体管之间建立背栅电压差来调整所产生的关于参考信号的滞后特性的定位。 还提供了一种开关电路，用于控制滞后电路在参考信号加或减所需偏移的切换。 开关电路由输入晶体管的输出信号选通。
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公开(公告)号：US06177809B1
公开(公告)日：2001-01-23
申请号：US09322470
申请日：1999-05-28
申请人： William R. Tonti , Jack A. Mandelman , Anthony R. Bonaccio , Claude L. Bertin , Howard L. Kalter , John A. Fifield
发明人： William R. Tonti , Jack A. Mandelman , Anthony R. Bonaccio , Claude L. Bertin , Howard L. Kalter , John A. Fifield
IPC分类号： H03K19094
CPC分类号： H03K19/00384 , H03K19/0005
摘要： A first, “known good” reference off-chip driver circuit actuated by an initial logic program (IPL) input signal has an output lead connected as one of the inputs to a comparator circuit for providing a reference off-chip driver output signal. A second off-chip driver circuit including a plurality of “n” separate driver circuit paths connected to input signal and produces output signals connected to a common node to provide output driver signals to the common node. The common node is connected to the second input of the comparator circuit for comparison with the reference off-chip driver output signal from the first off-chip driver circuit to determine the operating state of the second off-chip driver circuit with respect to the operating state of the first off-chip driver circuit.
摘要翻译： 由初始逻辑程序（IPL）输入信号驱动的第一个“已知的良好”参考芯片外驱动电路具有作为输入端之一的输出引线连接到比较器电路，用于提供参考片外驱动器输出信号。 包括连接到输入信号的多个“n”个分离的驱动器电路路径并产生连接到公共节点的输出信号以向公共节点提供输出驱动器信号的第二片外驱动器电路。 公共节点连接到比较器电路的第二输入，用于与来自第一片外驱动器电路的参考芯片外驱动器输出信号进行比较，以确定第二片外驱动器电路相对于操作的运行状态 状态的第一个片外驱动电路。
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公开(公告)号：US06177807B1
公开(公告)日：2001-01-23
申请号：US09322465
申请日：1999-05-28
IPC分类号： G03K1716
CPC分类号： G06F13/4086 , H03K5/06 , H04L25/0298
摘要： A processor with a memory send/received control circuit including a bus drive circuit and a detector circuit connected via control bus line to the control input of the memory. A data input line, or output line, or data input/output line is connected between the processor and the memory. A transmission line stub having a length that is incrementally variable is connected to the memory control input side of the control line 14. The impedance Z0 of the transmission line stub is equal to that of the control line and is open circuited at the end which results in voltage doubling to achieve high speed synchronization between control signals and data signals and to ensure valid data at high clock rates.
摘要翻译： 具有存储器发送/接收控制电路的处理器，包括总线驱动电路和经由控制总线连接到存储器的控制输入端的检测器电路。 数据输入线或输出线或数据输入/输出线连接在处理器和存储器之间。 具有递增可变长度的传输线短截线连接到控制线14的存储器控制输入侧。传输线短截线的阻抗Z0等于控制线的阻抗Z0，并在结束时开路 在电压倍增以实现控制信号和数据信号之间的高速同步，并确保在高时钟速率下的有效数据。
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公开(公告)号：US06268748B1
公开(公告)日：2001-07-31
申请号：US09073517
申请日：1998-05-06
申请人： Claude L. Bertin , John A. Fifield , Russell J. Houghton , Christopher P. Miller , William R. Tonti
发明人： Claude L. Bertin , John A. Fifield , Russell J. Houghton , Christopher P. Miller , William R. Tonti
IPC分类号： G03K19094
CPC分类号： G11C7/1069 , G11C7/1051 , H03K19/0016 , H03K19/09429
摘要： An electronic semiconductor module, either memory or logic, having a driver circuit which includes a multiplicity of driver transistors, together with circuitry for simultaneously applying a first positive bias to a first select number of driver transistors to activate them to an operational state, a second positive bias to a second select number of driver transistors to place them in readiness for activation, and a negative bias to the remaining driver transistors to place them in a fully inactive state thereby reducing noise in the driver circuit. The first positive bias is greater than the transistor threshold voltage, preferably greater than two volts, the second positive bias is less than the threshold voltage, preferably less than one volt, and the negative bias is in the order of minus 0.3 volt. A method of reducing noise in the electronic semiconductor module is also described and includes the applying of a positive bias to a first select number of the transistors to activate them while simultaneously applying a second positive bias to a second select number of the transistors to ready them for activation, and a negative voltage to the remaining transistors to place each in a inactive condition.
摘要翻译： 一种电子半导体模块，无论是存储器还是逻辑，具有包括多个驱动器晶体管的驱动器电路，以及用于同时向第一选择数量的驱动器晶体管施加第一正偏置以将其激活到操作状态的电路，第二 对第二选择数量的驱动器晶体管施加正偏置以使它们准备激活，以及对其余驱动器晶体管的负偏置以将它们置于完全无效状态，从而降低驱动器电路中的噪声。 第一正偏压大于晶体管阈值电压，优选大于2伏，第二正偏压小于阈值电压，优选小于1伏特，负偏压为零下0.3伏。 还描述了降低电子半导体模块中的噪声的方法，并且包括将正偏压施加到第一选择数量的晶体管以激活它们，同时向第二选择数量的晶体管施加第二正偏置以准备它们 用于激活，并且向剩余晶体管施加负电压以使其处于非活动状态。
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公开(公告)号：US5757693A
公开(公告)日：1998-05-26
申请号：US803056
申请日：1997-02-19
申请人： Russell J. Houghton , Claude L. Bertin , John A. Fifield , Christopher P. Miller , William R. Tonti
发明人： Russell J. Houghton , Claude L. Bertin , John A. Fifield , Christopher P. Miller , William R. Tonti
IPC分类号： G11C11/402 , G11C11/403 , G11C11/405 , G11C11/24
CPC分类号： G11C11/405 , G11C11/403
摘要： A gain cell in a memory array having read and write bitlines and wordlines, wherein the gain cell comprises a write transistor, a storage node, a read transistor, and a diode is disclosed. The write transistor allows the value of the write bitline to be stored onto the storage node when activated by the write wordline. The read transistor, which allows the stored value to be read, is coupled to the storage node and to the read bitline via the diode. The diode prevents the conduction of the read transistor in the opposite direction, thus preventing read interference from other cells and reducing bitline capacitance.
摘要翻译： 具有读和写位线和字线的存储器阵列中的增益单元，其中增益单元包括写晶体管，存储节点，读晶体管和二极管。 当由写入字线激活时，写入晶体管允许将写入位线的值存储到存储节点上。 允许读取存储值的读取晶体管通过二极管耦合到存储节点和读取位线。 二极管防止读取晶体管在相反方向的导通，从而防止来自其他单元的读取干扰并减少位线电容。
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公开(公告)号：US06346846B1
公开(公告)日：2002-02-12
申请号：US09466479
申请日：1999-12-17
申请人： Claude L. Bertin , John A. Fifield , Russell J. Houghton , William R. Tonti , Nicholas M. Van Heel
发明人： Claude L. Bertin , John A. Fifield , Russell J. Houghton , William R. Tonti , Nicholas M. Van Heel
IPC分类号： H01H3776
摘要： Methods and apparatus for blowing and sensing antifuses are provided. Specifically, in a first aspect, a method is provided for changing the state of one of a plurality of antifuses by selecting one of the bank of antifuses and applying a high voltage to change the state of the selected antifuse. In second and third aspects, apparatus are provided for performing the method of the first aspect. In a fourth aspect, a method is provided for boosting a voltage that includes the steps of generating a first voltage within a first stage storage mechanism of a first stage voltage booster circuit, generating a second voltage equaling about twice the first voltage within a first and a second, second stage storage mechanism of a second stage voltage booster circuit, and generating about thrice the first voltage based on the second voltage of the second stage voltage booster circuit. In a fifth aspect, apparatus are provided for performing the method of the fourth aspect.
摘要翻译： 提供了用于吹制和检测反熔丝的方法和装置。 具体地，在第一方面中，提供一种通过选择一组反熔丝中的一个并且施加高电压来改变所选择的反熔丝的状态来改变多个反熔丝之一的状态的方法。 在第二和第三方面中，提供了用于执行第一方面的方法的装置。 在第四方面，提供了一种用于升压电压的方法，包括以下步骤：在第一级升压电路的第一级存储机构内产生第一电压，产生等于第一级升压电路中第一电压的大约两倍的第二电压， 第二级升压电路的第二级第二级存储机构，并且基于第二级升压电路的第二电压产生约三倍的第一电压。 在第五方面中，提供了用于执行第四方面的方法的装置。
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9.发明授权Capacitive precharging and discharging network for converting N bit input into M bit output 失效用于将N位输入转换为M位输出的电容式预充放电网络公开(公告)号：US06195027B1
公开(公告)日：2001-02-27
申请号：US09302744
申请日：1999-04-30
申请人： Claude L. Bertin , John A. Fifield , Russell J. Houghton , Christopher P. Miller , Steven W. Tomashot , William R. Tonti
发明人： Claude L. Bertin , John A. Fifield , Russell J. Houghton , Christopher P. Miller , Steven W. Tomashot , William R. Tonti
IPC分类号： H03M720
CPC分类号： G11C8/10
摘要： A method and structure for decoding n input signals and their complements to one of m output signals is provided. A capacitive network is provided having m output nodes. The output nodes are precharged to a given voltage value. N input signals and their complements are provided each having either a high value or a low value. At least one but less than all of the output nodes are discharged to a value less than the given voltage but greater than ground in output patterns responsive to given input patterns of the true and complement values of the input signals. The output patterns of the discharged nodes is such as to provide one and only one discharged or one and only one undischarged node for any given pattern of input signals. Preferably the capacitive network includes NMOS inversion capacitors.
摘要翻译： 提供了用于将n个输入信号及其与m个输出信号之一的补码进行解码的方法和结构。 提供具有m个输出节点的电容网络。 输出节点预充电到给定的电压值。 提供N个输入信号及其补码，每个具有高值或低值。 响应于输入信号的真值和补码值的给定输入模式，至少一个但不到所有输出节点的输出模式被放电到小于给定电压但大于输出模式的输出值的值。 放电节点的输出模式是为任何给定模式的输入信号提供一个且仅一个放电或一个且仅一个未充电节点。 优选地，电容网络包括NMOS反转电容器。
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公开(公告)号：US5761114A
公开(公告)日：1998-06-02
申请号：US803034
申请日：1997-02-19
申请人： Claude L. Bertin , John A. Fifield , Russell J. Houghton , Christopher P. Miller , William R. Tonti
发明人： Claude L. Bertin , John A. Fifield , Russell J. Houghton , Christopher P. Miller , William R. Tonti
IPC分类号： G11C11/56
CPC分类号： G11C11/565 , G11C16/30
摘要： A method and apparatus for using multi-level signals in a gain cell is shown. The method involves of first, storing a value of a multi-level signal in the gain cell. A stepping waveform is then applied to the gain cell and the gain cell outputs a conduction signal when the level of the stepping waveform corresponds to the value of the multilevel signal that is stored within the gain cell. Finally, the value of the multi-level signal is determined through the conduction signal and the corresponding level of the stepping waveform. The gain cell includes an input device, a storage device and a level comparator, which responds to the stepping waveform generated from a stepping signal generator and outputs the conduction signal for determining the value of the multi-level signal stored in the storage device.
摘要翻译： 示出了在增益单元中使用多电平信号的方法和装置。 该方法首先在增益单元中存储多电平信号的值。 然后，当增益单元的步进波形对应于存储在增益单元内的多电平信号的值时，增益单元输出导通信号。 最后，通过导通信号和步进波形的相应电平来确定多电平信号的值。 增益单元包括响应于从步进信号发生器产生的步进波形的输入装置，存储装置和电平比较器，并输出用于确定存储在存储装置中的多电平信号的值的导通信号。
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