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公开(公告)号：US20190198125A1
公开(公告)日：2019-06-27
申请号：US16208841
申请日：2018-12-04
发明人： James Pak , Shivananda Shetty , Yoram Betser , Amichai Givant , Jonas Neo , Pawan Singh , Stefano Amato , Cindy Sun , Amir Rochman
摘要： A non-volatile memory device and methods for operating the same are provided. The memory device may have multiple complementary memory cells. The method of blank check includes detecting a state value of each of the true and complementary transistors, generating an upper state value, Wherein a first predetermined amount of the true and complementary transistors have greater state values than the upper state value, generating a lower state value, wherein a second predetermined amount of the true and complementary transistors have less state values than the lower state value, generating a state value range based on a difference between the upper state value and the lower state value, and comparing the state value range to a threshold value to determine whether the plurality of complementary memory cells is in a blank state or a non-blank state. Other embodiments are also disclosed herein.
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公开(公告)号：US10141065B1
公开(公告)日：2018-11-27
申请号：US15850779
申请日：2017-12-21
发明人： Kobi Danon , Yoram Betser , Uri Kotlicki , Arieh Feldman
摘要： A semiconductor device comprises an embedded flash memory with row redundancy. The embedded flash memory comprises a memory bank that includes multiple physical sectors, where each physical sector comprises a plurality of erase sectors. In the memory bank, multiple portions of an additional erase sector are respectively distributed among the multiple physical sectors. The multiple portions of the additional erase sector are configured as a row-redundancy sector for the memory bank.
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公开(公告)号：US20180261295A1
公开(公告)日：2018-09-13
申请号：US15954955
申请日：2018-04-17
发明人： Chun Chen , Yoram Betser , Kuo Tung Chang , Amichai GIVANT , Shivananda Shetty , Shenqing Fang
IPC分类号： G11C16/34 , G11C11/56 , G11C16/10 , H01L27/115 , G11C16/04
CPC分类号： G11C16/3427 , G11C11/5628 , G11C11/5642 , G11C16/0425 , G11C16/0466 , G11C16/0483 , G11C16/10 , H01L27/115 , H01L27/11568 , H01L29/42344
摘要： A memory device includes a memory array arranged in rows and columns. The memory array may have at least four non-volatile memory (NVM) cells coupled in the same column of the memory array, in which each NVM cell may include a memory gate. The first and second NVM cells of the at least four NVM cells may share a first source region, and the third and fourth NVM cells may share a second source region. The memory gates of the first and second NVM cells may not be electrically coupled with one another, and the first and second source regions may not be electrically coupled with one another. Each of the first and second source regions may be electrically coupled with at least another source region of the same column in the memory array.
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4.发明申请公开(公告)号：US20210042245A1
公开(公告)日：2021-02-11
申请号：US16719493
申请日：2019-12-18
发明人： Yoram Betser , Cliff Zitlaw , Stephan Rosner , Kobi Danon , Amir Rochman
摘要： A nonvolatile memory device can include a serial port having at least one serial clock input, and at least one serial data input/output (I/O) configured to receive command, address and write data in synchronism with the at least one serial clock input. At least one parallel port can include a plurality of command address inputs configured to receive command and address data in groups of parallel bits and a plurality of unidirectional data outputs configured to output read data in parallel on rising and falling edges of a data clock signal. Each of a plurality of banks can include nonvolatile memory cells and be configurable for access by the serial port or the parallel port. When a bank is configured for access by the serial port, the bank is not accessible by the at least one parallel port. Related methods and systems are also disclosed.
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公开(公告)号：US10304545B2
公开(公告)日：2019-05-28
申请号：US15995926
申请日：2018-06-01
摘要： Disclosed is a non-volatile memory (NVM) device including an array of NVM cells segmented into at least a first sector and a second sector and at least one sensing circuit to sense a state of a target NVM cell in the first sector using a reference current of the second sector received from at least a dynamic reference cell.
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公开(公告)号：US09773529B1
公开(公告)日：2017-09-26
申请号：US15279974
申请日：2016-09-29
发明人： Kobi Danon , Yoram Betser , Alex Kushnarenko
CPC分类号： G11C7/062 , G11C16/26 , G11C16/28 , G11C2211/4013
摘要： A method for operating a read command of N complementary memory cells, the method includes the steps of determining if each of the first and second memory cells of the N complementary memory cells is in a first binary state or a second binary state, generating a count value by counting a total number of the first and second memory cells that are in the first binary state, and determining if the N complementary memory cells are programmed or erased based on a result of comparing the count value to a threshold number.
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7.发明授权公开(公告)号：US11449441B2
公开(公告)日：2022-09-20
申请号：US17327460
申请日：2021-05-21
发明人： Yoram Betser , Cliff Zitlaw , Stephan Rosner , Kobi Danon , Amir Rochman
摘要： A memory device that includes a first port and a second port. The first port includes a first clock input, at least one first command address input, and at least one data input or output configured to transfer data in relation to the memory device. The second port includes a second clock input and at least one command, address, and data input/output (I/O) configured to receive command and address information from, and to transfer data in relation to the memory device. The memory device also includes a plurality of memory banks, in which two different memory banks may be accessed respectively by the first and the second ports concurrently. Other embodiments of the memory device and related methods and systems are also disclosed.
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8.发明授权公开(公告)号：US11030128B2
公开(公告)日：2021-06-08
申请号：US16719493
申请日：2019-12-18
发明人： Yoram Betser , Cliff Zitlaw , Stephan Rosner , Kobi Danon , Amir Rochman
摘要： A nonvolatile memory device can include a serial port having at least one serial clock input, and at least one serial data input/output (I/O) configured to receive command, address and write data in synchronism with the at least one serial clock input. At least one parallel port can include a plurality of command address inputs configured to receive command and address data in groups of parallel bits and a plurality of unidirectional data outputs configured to output read data in parallel on rising and falling edges of a data clock signal. Each of a plurality of banks can include nonvolatile memory cells and be configurable for access by the serial port or the parallel port. When a bank is configured for access by the serial port, the bank is not accessible by the at least one parallel port. Related methods and systems are also disclosed.
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公开(公告)号：US20200303023A1
公开(公告)日：2020-09-24
申请号：US16867828
申请日：2020-05-06
发明人： Chun Chen , Kuo Tung Chang , Yoram Betser , Shivananda Shetty , Giovanni Mazzeo , Tio Wei Neo , Pawan Singh
IPC分类号： G11C16/34 , G11C16/30 , G11C16/04 , G11C16/10 , G11C7/04 , G11C16/24 , G11C16/16 , G11C16/26
摘要： Techniques for suppression of program disturb in flash memory devices are described herein. In an example embodiment, a method for suppression of program disturb in a flash memory array is provided. The flash memory array comprises rows and columns of memory cells, where the memory cells in each row are coupled to a source line and to a select-gate (SG) line, and the memory cells in each column are coupled to a respective bit line (BL). During a program memory operation, a first voltage, of a selected SG line, and a second voltage, of an unselected BL, are regulated independently of a power supply voltage of the flash memory array, where the first voltage is regulated in a first range of 0.9V to 1.1V and the second voltage is regulated in a second range of 0.4V to 1.2V.
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公开(公告)号：US10679712B2
公开(公告)日：2020-06-09
申请号：US16208841
申请日：2018-12-04
发明人： James Pak , Shivananda Shetty , Yoram Betser , Amichai Givant , Jonas Neo , Pawan Singh , Stefano Amato , Cindy Sun , Amir Rochman
摘要： A non-volatile memory device and methods for operating the same are provided. The memory device may have multiple complementary memory cells. The method of blank check includes detecting a state value of each of the true and complementary transistors, generating an upper state value, Wherein a first predetermined amount of the true and complementary transistors have greater state values than the upper state value, generating a lower state value, wherein a second predetermined amount of the true and complementary transistors have less state values than the lower state value, generating a state value range based on a difference between the upper state value and the lower state value, and comparing the state value range to a threshold value to determine whether the plurality of complementary memory cells is in a blank state or a non-blank state. Other embodiments are also disclosed herein.
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