公开(公告)号：US20120009771A1

公开(公告)日：2012-01-12

申请号：US12833272

申请日：2010-07-09

申请人： Cyril Cabral, JR. ,  John M. Cotte ,  Dinesh R. Koli ,  Laura L. Kosbar ,  Mahadevaiyer Krishnan ,  Christian Lavoie ,  Stephen M. Rossnagel ,  Zhen Zhang

发明人： Cyril Cabral, JR. ,  John M. Cotte ,  Dinesh R. Koli ,  Laura L. Kosbar ,  Mahadevaiyer Krishnan ,  Christian Lavoie ,  Stephen M. Rossnagel ,  Zhen Zhang

IPC分类号： H01L21/3205

CPC分类号： H01L21/28512 ,  H01L21/28518 ,  H01L29/456

摘要： A method for formation of a segregated interfacial dopant layer at a junction between a semiconductor material and a silicide layer includes depositing a doped metal layer over the semiconductor material; annealing the doped metal layer and the semiconductor material, wherein the anneal causes a portion of the doped metal layer and a portion of the semiconductor material to react to form the silicide layer on the semiconductor material, and wherein the anneal further causes the segregated interfacial dopant layer to form between the semiconductor material and the silicide layer, the segregated interfacial dopant layer comprising dopants from the doped metal layer; and removing an unreacted portion of the doped metal layer from the silicide layer.

摘要翻译： 在半导体材料和硅化物层之间的结处形成分离的界面掺杂剂层的方法包括在半导体材料上沉积掺杂的金属层; 退火所述掺杂金属层和所述半导体材料，其中所述退火使所述掺杂金属层的一部分和所述半导体材料的一部分反应以在所述半导体材料上形成所述硅化物层，并且其中所述退火还导致所述分离的界面掺杂剂 层，以形成在半导体材料和硅化物层之间，分离的界面掺杂剂层包含来自掺杂金属层的掺杂剂; 以及从所述硅化物层去除所述掺杂金属层的未反应部分。

公开(公告)号：US08889537B2

公开(公告)日：2014-11-18

申请号：US12833272

申请日：2010-07-09

申请人： Cryil Cabral, Jr. ,  John M. Cotte ,  Dinesh R. Koli ,  Laura L. Kosbar ,  Mahadevaiyer Krishnan ,  Christian Lavoie ,  Stephen M. Rossnagel ,  Zhen Zhang

发明人： Cryil Cabral, Jr. ,  John M. Cotte ,  Dinesh R. Koli ,  Laura L. Kosbar ,  Mahadevaiyer Krishnan ,  Christian Lavoie ,  Stephen M. Rossnagel ,  Zhen Zhang

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L29/45

CPC分类号： H01L21/28512 ,  H01L21/28518 ,  H01L29/456

摘要： A method for formation of a segregated interfacial dopant layer at a junction between a semiconductor material and a silicide layer includes depositing a doped metal layer over the semiconductor material; annealing the doped metal layer and the semiconductor material, wherein the anneal causes a portion of the doped metal layer and a portion of the semiconductor material to react to form the silicide layer on the semiconductor material, and wherein the anneal further causes the segregated interfacial dopant layer to form between the semiconductor material and the silicide layer, the segregated interfacial dopant layer comprising dopants from the doped metal layer; and removing an unreacted portion of the doped metal layer from the silicide layer.

摘要翻译： 在半导体材料和硅化物层之间的结处形成分离的界面掺杂剂层的方法包括在半导体材料上沉积掺杂的金属层; 退火所述掺杂金属层和所述半导体材料，其中所述退火使所述掺杂金属层的一部分和所述半导体材料的一部分反应以在所述半导体材料上形成所述硅化物层，并且其中所述退火还导致所述分离的界面掺杂剂 层，以形成在半导体材料和硅化物层之间，分离的界面掺杂剂层包含来自掺杂金属层的掺杂剂; 以及从所述硅化物层去除所述掺杂金属层的未反应部分。

公开(公告)号：US20120038048A1

公开(公告)日：2012-02-16

申请号：US12854506

申请日：2010-08-11

申请人： Cyril Cabral, JR. ,  Benjamin Fletcher ,  Christian Lavoie ,  Zhen Zhang

发明人： Cyril Cabral, JR. ,  Benjamin Fletcher ,  Christian Lavoie ,  Zhen Zhang

IPC分类号： H01L23/532 ,  H01L21/3205

CPC分类号： H01L21/76885 ,  H01L21/265 ,  H01L21/76886 ,  H01L29/78

摘要： A method of forming nickel monosilicide is provided that includes providing a silicon-containing surface, and ion implanting carbon into the silicon-containing surface.A nickel-containing layer is formed on the silicon-containing surface. Alloying the nickel-containing surface and the silicon-containing surface layer to provide a nickel monosilicide. The present disclosure also provides a non-agglomerated Ni monosilicide contact that includes a carbon interstitial dopant present in a concentration ranging from 1×1019 atoms/cm3 to 1×1021 atoms/cm3.

摘要翻译： 提供一种形成一硅酸镍的方法，其包括提供含硅表面和将离子注入到含硅表面中的碳。 在含硅表面上形成含镍层。 合金化含镍表面和含硅表面层，以提供镍一硅化镍。 本公开还提供了非聚集的Ni单硅化物接触，其包括以1×1019原子/ cm3至1×1021原子/ cm3的浓度存在的碳间隙掺杂剂。

公开(公告)号：US08859316B2

公开(公告)日：2014-10-14

申请号：US12825527

申请日：2010-06-29

申请人： Dechao Guo ,  Christian Lavoie ,  Christine Ouyang Qiqing ,  Yanning Sun ,  Zhen Zhang

发明人： Dechao Guo ,  Christian Lavoie ,  Christine Ouyang Qiqing ,  Yanning Sun ,  Zhen Zhang

IPC分类号： H01L21/00 ,  H01L29/06 ,  G01N27/414

CPC分类号： G01N27/4145 ,  G01N27/4146 ,  H01L29/0673

摘要： A Schottky junction silicon nanowire field-effect biosensor/molecule detector with a nanowire thickness of 10 nanometer or less and an aligned source/drain workfunction for increased sensitivity. The nanowire channel is coated with a surface treatment to which a molecule of interest absorbs, which modulates the conductivity of the channel between the Schottky junctions sufficiently to qualitatively and quantitatively measure the presence and amount of the molecule.

摘要翻译： 肖特基结的硅纳米线场效应生物传感器/分子检测器，纳米线厚度为10纳米或更小，并具有对准的源极/漏极功能，以提高灵敏度。 纳米线通道涂覆有目标分子吸收的表面处理，其可以充分调节肖特基结之间的通道的电导率以定性和定量地测量分子的存在和量。

公开(公告)号：US08741753B2

公开(公告)日：2014-06-03

申请号：US13611736

申请日：2012-09-12

申请人： Kisik Choi ,  Christian Lavoie ,  Paul M. Solomon ,  Bin Yang ,  Zhen Zhang

发明人： Kisik Choi ,  Christian Lavoie ,  Paul M. Solomon ,  Bin Yang ,  Zhen Zhang

IPC分类号： H01L21/20 ,  H01L21/3205 ,  H01L21/00

CPC分类号： H01L29/7833 ,  H01L21/28512 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545

摘要： A device includes a gate stack formed over a channel in a semiconductor substrate. The gate stack includes a layer of gate insulator material, a layer of gate metal overlying the layer of gate insulator material, and a layer of contact metal overlying the layer band edge gate metal. The device further includes source and drain contacts adjacent to the channel. The source and drain contacts each include a layer of the gate metal that overlies and is in direct electrical contact with a doped region of the semiconductor substrate, and a layer of contact metal that overlies the layer of gate metal.

摘要翻译： 一种器件包括形成在半导体衬底中的沟道上方的栅叠层。 栅极堆叠包括栅极绝缘体材料层，覆盖栅极绝缘体材料层的栅极金属层和覆盖层带边缘栅极金属的接触金属层。 该装置还包括邻近通道的源极和漏极接触。 源极和漏极触点各自包括覆盖并与半导体衬底的掺杂区域直接电接触的栅极金属层以及覆盖在栅极金属层上的接触金属层。

公开(公告)号：US08456011B2

公开(公告)日：2013-06-04

申请号：US13006664

申请日：2011-01-14

申请人： Christian Lavoie ,  Ahmet S. Ozcan ,  Zhen Zhang ,  Bin Yang

发明人： Christian Lavoie ,  Ahmet S. Ozcan ,  Zhen Zhang ,  Bin Yang

IPC分类号： H01L23/532

CPC分类号： H01L21/768 ,  H01L21/28518 ,  H01L23/485 ,  H01L29/456 ,  H01L29/66545 ,  H01L29/66575 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a metal semiconductor alloy that includes forming an intermixed metal semiconductor region to a first depth of a semiconductor substrate without thermal diffusion. The intermixed metal semiconductor region is annealed to form a textured metal semiconductor alloy. A second metal layer is formed on the textured metal semiconductor alloy. The second metal layer on the textured metal semiconductor alloy is then annealed to form a metal semiconductor alloy contact, in which metal elements from the second metal layer are diffused through the textured metal semiconductor alloy to provide a templated metal semiconductor alloy. The templated metal semiconductor alloy includes a grain size that is greater than 2× for the metal semiconductor alloy, which has a thickness ranging from 15 nm to 50 nm.

公开(公告)号：US08278200B2

公开(公告)日：2012-10-02

申请号：US13012043

申请日：2011-01-24

申请人： Christian Lavoie ,  Tak H. Ning ,  Ahmet S. Ozcan ,  Bin Yang ,  Zhen Zhang

发明人： Christian Lavoie ,  Tak H. Ning ,  Ahmet S. Ozcan ,  Bin Yang ,  Zhen Zhang

IPC分类号： H01L21/20

CPC分类号： H01L21/28518

摘要： In one exemplary embodiment, a program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine for performing operations, said operations including: depositing a first layer having a first metal on a surface of a semiconductor structure, where depositing the first layer creates a first intermix region at an interface of the first layer and the semiconductor structure; removing a portion of the deposited first layer to expose the first intermix region; depositing a second layer having a second metal on the first intermix region, where depositing the second layer creates a second intermix region at an interface of the second layer and the first intermix region; removing a portion of the deposited second layer to expose the second intermix region; and performing at least one anneal on the semiconductor structure.

摘要翻译： 在一个示例性实施例中，一种可由机器读取的程序存储设备，其有形地体现了可由机器执行的用于执行操作的指令程序，所述操作包括：在半导体结构的表面上沉积具有第一金属的第一层， 第一层在第一层和半导体结构的界面处形成第一混合区; 去除沉积的第一层的一部分以暴露第一混合区; 在所述第一混合区域上沉积具有第二金属的第二层，其中沉积所述第二层在所述第二层和所述第一混合区的界面处产生第二混合区; 去除沉积的第二层的一部分以暴露第二混合区; 以及在所述半导体结构上执行至少一个退火。

公开(公告)号：US08168503B2

公开(公告)日：2012-05-01

申请号：US12726736

申请日：2010-03-18

申请人： Marwan H. Khater ,  Christian Lavoie ,  Bin Yang ,  Zhen Zhang

发明人： Marwan H. Khater ,  Christian Lavoie ,  Bin Yang ,  Zhen Zhang

IPC分类号： H01L21/336

CPC分类号： H01L29/7839 ,  H01L29/78654

摘要： A method of fabricating a Schottky field effect transistor is provided that includes providing a substrate having at least a first semiconductor layer overlying a dielectric layer, wherein the first semiconductor layer has a thickness of less than 10.0 nm. A gate structure is formed directly on the first semiconductor layer. A raised semiconductor material is selectively formed on the first semiconductor layer adjacent to the gate structure. The raised semiconductor material is converted into Schottky source and drain regions composed of a metal semiconductor alloy. A non-reacted semiconductor material is present between the Schottky source and drain regions and the dielectric layer.

摘要翻译： 提供一种制造肖特基场效应晶体管的方法，其包括提供具有覆盖在电介质层上的至少第一半导体层的衬底，其中第一半导体层具有小于10.0nm的厚度。 栅极结构直接形成在第一半导体层上。 凸起的半导体材料选择性地形成在与栅极结构相邻的第一半导体层上。 凸起的半导体材料被转换成由金属半导体合金构成的肖特基源极和漏极区域。 在肖特基源极和漏极区域与电介质层之间存在未反应的半导体材料。

公开(公告)号：US09099327B2

公开(公告)日：2015-08-04

申请号：US13568839

申请日：2012-08-07

申请人： Wilfried Haensch ,  Christian Lavoie ,  Christine Qiqing Ouyang ,  Xiaoyan Shao ,  Paul M. Solomon ,  Zhen Zhang ,  Bin Yang

发明人： Wilfried Haensch ,  Christian Lavoie ,  Christine Qiqing Ouyang ,  Xiaoyan Shao ,  Paul M. Solomon ,  Zhen Zhang ,  Bin Yang

IPC分类号： H01L29/06 ,  H01L21/8238 ,  H01L29/417

CPC分类号： H01L29/0673 ,  H01L21/823814 ,  H01L29/41791

摘要： A multigate structure which comprises a semiconductor substrate; an ultra-thin silicon or carbon bodies of less than 20 nanometers thick located on the substrate; an electrolessly deposited metallic layer selectively located on the side surfaces and top surfaces of the ultra-thin silicon or carbon bodies and selectively located on top of the multigate structures to make electrical contact with the ultra-thin silicon or carbon bodies and to minimize parasitic resistance, and wherein the ultra-thin silicon or carbon bodies and metallic layer located thereon form source and drain regions is provided along with a process to fabricate the structure.

摘要翻译： 一种多栅格结构，包括半导体衬底; 位于基板上的小于20纳米厚的超薄硅或碳体; 选择性地位于超薄硅或碳体的侧表面和顶表面上的无电沉积金属层，并且选择性地位于多结构结构的顶部上以与超薄硅或碳体电接触并最小化寄生电阻 并且其中位于其上的超薄硅或碳体和金属层形成源区和漏区以及制造该结构的工艺。

公开(公告)号：US20130249099A1

公开(公告)日：2013-09-26

申请号：US13428184

申请日：2012-03-23

申请人： Christian Lavoie ,  Dong-Ick Lee ,  Ahmet Serkan Ozcan ,  Zhen Zhang

发明人： Christian Lavoie ,  Dong-Ick Lee ,  Ahmet Serkan Ozcan ,  Zhen Zhang

IPC分类号： H01L23/48 ,  H01L21/336 ,  H01L21/28

CPC分类号： H01L29/665 ,  H01L21/02381 ,  H01L21/02631 ,  H01L21/244 ,  H01L21/28518 ,  H01L21/32133 ,  H01L21/324 ,  H01L29/161

摘要： In one aspect, a method of fabricating a metal silicide includes the following steps. A semiconductor material selected from the group consisting of silicon and silicon germanium is provided. A metal(s) is deposited on the semiconductor material. A first anneal is performed at a temperature and for a duration sufficient to react the metal(s) with the semiconductor material to form an amorphous layer including an alloy formed from the metal(s) and the semiconductor material, wherein the temperature at which the first anneal is performed is below a temperature at which a crystalline phase of the alloy is formed. An etch is used to selectively remove unreacted portions of the metal(s). A second anneal is performed at a temperature and for a duration sufficient to crystallize the alloy thus forming the metal silicide. A device contact and a method of fabricating a FET device are also provided.