利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

23 条记录 (耗时 0.045 秒)

    Method for forming a TiN layer on top of a metal silicide layer in a semiconductor structure and structure formed
    1.
    发明授权
    Method for forming a TiN layer on top of a metal silicide layer in a semiconductor structure and structure formed 有权
    在半导体结构中的金属硅化物层的顶部上形成TiN层的方法和形成的结构

    公开(公告)号：US06436823B1

    公开(公告)日：2002-08-20

    申请号：US09679738

    申请日：2000-10-05

    申请人： Cyril Cabral, Jr. ,  Chung-Ping Eng ,  Lynne Marie Gignac ,  Christian Lavoie ,  Patricia O'Neil ,  Kirk David Peterson ,  Tina Wagner ,  Yun-Yu Wang ,  Keith Wong

    发明人： Cyril Cabral, Jr. ,  Chung-Ping Eng ,  Lynne Marie Gignac ,  Christian Lavoie ,  Patricia O'Neil ,  Kirk David Peterson ,  Tina Wagner ,  Yun-Yu Wang ,  Keith Wong

    IPC分类号： H01L2144

    CPC分类号： H01L21/76856 ,  H01L21/28518 ,  H01L2221/1078

    摘要： A method for forming a TiN layer on top of a metal silicide layer in a semiconductor structure without the formation of a thick amorphous layer containing Ti, Co and Si and the structure formed are provided. In the method, after a Ti layer is deposited on top of a metal silidide layer, a dual-step annealing process is conducted in which a low temperature annealing in a forming gas (or ammonia) at a temperature not higher than 500° C. is first conducted for less than 2 hours followed by a high temperature annealing in a nitrogen-containing gas (or ammonia) at a second temperature not lower than 500° for less than 2 hours to form the TiN layer. The present invention method prevents the problem usually caused by a thick amorphous material layer of Ti—Si—Co which produces weakly bonded Ti which reacts with fluorine atoms from WF6 during a subsequent CVD W deposition process and causes liner failure due to a volume expansion of the amorphous material. The maximum thickness of the amorphous material layer formed by the present invention method is less than 5 nm which minimizes the line failure problem.

    摘要翻译： 提供了一种在半导体结构中的金属硅化物层的顶部上形成TiN层的方法，而不形成含有Ti，Co和Si的厚非晶层以及形成的结构。 在该方法中，在金属硅化物层的顶部沉积Ti层之后，进行双相退火工艺，其中在不高于500℃的温度下在成形气体（或氨）中进行低温退火。 首先进行少于2小时，然后在不低于500℃的第二温度下在含氮气体（或氨）中进行低温退火2小时以形成TiN层。 本发明的方法防止了在随后的CVD W沉积过程中由Ti-Si-Co的厚的无定形材料层产生的弱结合的Ti与来自WF6的氟原子反应而产生的弱结合的问题，并导致由于体积膨胀引起的衬管故障 无定形材料。 通过本发明方法形成的非晶材料层的最大厚度小于5nm，这使线路故障问题最小化。

    Protect diodes for hybrid-orientation substrate structures
    5.
    发明授权
    Protect diodes for hybrid-orientation substrate structures 失效
    用于混合取向衬底结构的保护二极管

    公开(公告)号：US07687340B2

    公开(公告)日：2010-03-30

    申请号：US11849489

    申请日：2007-09-04

    申请人： James William Adkisson ,  Jeffrey Peter Gambino ,  Alain Loiseau ,  Kirk David Peterson

    发明人： James William Adkisson ,  Jeffrey Peter Gambino ,  Alain Loiseau ,  Kirk David Peterson

    IPC分类号： H01L21/8234

    CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0255 ,  H01L27/0922 ,  H01L27/1207 ,  H01L29/045

    摘要： A semiconductor structure fabrication method. First, a semiconductor structure is provided including (a) a semiconductor block having a first semiconductor material doped with a first doping polarity and having a first lattice orientation, and (b) a semiconductor region on the semiconductor block, wherein the semiconductor region is physically isolated from the semiconductor block by a dielectric region, and wherein the semiconductor region includes a second semiconductor material (i) doped with a second doping polarity opposite to the first doping polarity and (ii) having a second lattice orientation different from the first lattice orientation. Next, first and second gate stacks are formed on the semiconductor block and the semiconductor region, respectively. Then, (i) first and second S/D regions are simultaneously formed in the semiconductor block on opposing sides of the first gate stack and (ii) first and second discharge prevention semiconductor regions in the semiconductor block.

    摘要翻译： 半导体结构制造方法。 首先，提供半导体结构，其包括：（a）具有掺杂有第一掺杂极性且具有第一晶格取向的第一半导体材料的半导体块，以及（b）半导体块上的半导体区域，其中半导体区域是物理上的 并且其中所述半导体区域包括掺杂有与所述第一掺杂极性相反的第二掺杂极性的第二半导体材料（i）和（ii）具有不同于所述第一晶格取向的第二晶格取向 。 接下来，分别在半导体块和半导体区域上形成第一和第二栅极叠层。 然后，（i）第一和第二S / D区域同时形成在半导体块中的第一栅极堆叠的相对侧上，以及（ii）半导体块中的第一和第二放电预防半导体区域。

    METHOD AND APPARATUS FOR IMPLEMENTING ENHANCED SRAM READ PERFORMANCE SORT RING OSCILLATOR (PSRO)
    6.
    发明申请
    METHOD AND APPARATUS FOR IMPLEMENTING ENHANCED SRAM READ PERFORMANCE SORT RING OSCILLATOR (PSRO) 有权
    实现增强SRAM读取性能分析振荡器（PSRO）的方法和设备

    公开(公告)号：US20090027946A1

    公开(公告)日：2009-01-29

    申请号：US11782808

    申请日：2007-07-25

    申请人： Chad Allen Adams ,  Todd Alan Christensen ,  Travis Reynold Hebig ,  Kirk David Peterson

    发明人： Chad Allen Adams ,  Todd Alan Christensen ,  Travis Reynold Hebig ,  Kirk David Peterson

    IPC分类号： G11C11/00

    CPC分类号： G11C11/413 ,  G11C11/41 ,  G11C11/419 ,  G11C2029/0403

    摘要： A method and apparatus including a static random access memory (SRAM) cell implement an enhanced SRAM read performance sort ring oscillator (PSRO). A pair of parallel reverse polarity connected inverters defines a static latch or cross-coupled memory cell. The SRAM cell includes independent left and right wordlines providing a respective gate input to a pair of access transistors used to access to the memory cell. The SRAM cell includes a voltage supply connection to one side of the static latch. For example, a complement side of the static latch is connected to the voltage supply. A plurality of the SRAM cells is assembled together to form a SRAM base block. A plurality of the SRAM base blocks is connected together to form the SRAM read PSRO.

    摘要翻译： 包括静态随机存取存储器（SRAM）单元的方法和装置实现增强型SRAM读取性能排序环形振荡器（PSRO）。 一对并联反极性连接的反相器定义了静态锁存器或交叉耦合存储器单元。 SRAM单元包括独立的左和右字线，为用于访问存储单元的一对存取晶体管提供相应的栅极输入。 SRAM单元包括到静态锁存器的一侧的电压供应连接。 例如，静态锁存器的补码侧连接到电源。 多个SRAM单元组装在一起以形成SRAM基块。 多个SRAM基块被连接在一起以形成SRAM读取PSRO。

    Cobalt disilicide structure
    7.
    发明授权
    Cobalt disilicide structure 失效
    二硅化钴结构

    公开(公告)号：US07411258B2

    公开(公告)日：2008-08-12

    申请号：US09939895

    申请日：2001-08-27

    申请人： David Paul Agnello ,  Mary Conroy Bushey ,  Donna K. Johnson ,  Jerome Brett Lasky ,  Peter James Lindgren ,  Kirk David Peterson

    发明人： David Paul Agnello ,  Mary Conroy Bushey ,  Donna K. Johnson ,  Jerome Brett Lasky ,  Peter James Lindgren ,  Kirk David Peterson

    IPC分类号： H01L29/76 ,  H01L29/94

    CPC分类号： H01L29/665 ,  H01L21/28518 ,  H01L21/31111 ,  H01L21/32134

    摘要： A structure relating to removal of an oxide of titanium generated as a byproduct of a process that forms cobalt disilicide within an insulated-gate field effect transistor (FET). The structure may comprise a layer of cobalt disilicide that is substantially free of cobalt monosilicide, with substantially no stringer of an oxide of titanium on the layer of cobalt disilicide. The structure may alternatively comprise a layer of cobalt disilicide, a patch of an oxide of titanium, and a reagent in contact with the patch at a temperature and for a period of time. The layer is substantially free of cobalt monosilicide. The patch is on the layer of cobalt disilicide. The reagent is adapted to remove the patch within the period of time. The reagent does not chemically react with the layer of cobalt disilicide, and the reagent comprises water, ammonium hydroxide, and hydrogen peroxide.

    摘要翻译： 涉及在绝缘栅场效应晶体管（FET）中除去作为形成二硅化钴的工艺的副产物的钛的氧化物的结构。 该结构可以包含基本上不含一钴硅酸钴的二硅化钴层，在二硅化钴层上基本上没有钛氧化物的桁条。 该结构可以可选地包括一层二硅化钴，一块钛的氧化物和在该温度和一段时间内与该贴片接触的试剂。 该层基本上不含一次硅化钴。 贴片在二硅化钴层上。 试剂适于在一段时间内除去贴剂。 试剂不与二硅化钴层发生化学反应，试剂包括水，氢氧化铵和过氧化氢。

    Cobal disilicide structure
    8.
    发明授权
    Cobal disilicide structure 失效
    钴二硅化物结构

    公开(公告)号：US07696586B2

    公开(公告)日：2010-04-13

    申请号：US12175549

    申请日：2008-07-18

    申请人： David Paul Agnello ,  Mary Conroy Bushey ,  Donna K. Johnson ,  Jerome Brett Lasky ,  Peter James Lindgren ,  Kirk David Peterson

    发明人： David Paul Agnello ,  Mary Conroy Bushey ,  Donna K. Johnson ,  Jerome Brett Lasky ,  Peter James Lindgren ,  Kirk David Peterson

    IPC分类号： H01L29/78 ,  H01L21/28

    CPC分类号： H01L29/665 ,  H01L21/28518 ,  H01L21/31111 ,  H01L21/32134

    摘要： A structure. The structure may include a layer of cobalt disilicide that is substantially free of cobalt monosilicide and there is substantially no stringer of an oxide of titanium on the layer of cobalt disilicide. The structure may include a substrate that includes: an insulated-gate field effect transistor (FET) that includes a source, a drain, and a gate; a first layer of cobalt disilicide on the source, said first layer having substantially no cobalt monosilicide, and said first layer having substantially no stringer of an oxide of titanium thereon; a second layer of cobalt disilicide on the drain, said second layer having substantially no cobalt monosilicide having substantially no stringer of an oxide of titanium thereon; and a third layer of cobalt disilicide on the gate, said third layer having substantially no cobalt monosilicide and having substantially no stringer of an oxide of titanium thereon.

    摘要翻译： 一个结构。 该结构可以包括基本上不含一钴硅酸钴的二硅化钴层，并且在二硅化钴层上基本上没有钛氧化物的桁条。 该结构可以包括：衬底，其包括：绝缘栅场效应晶体管（FET），其包括源极，漏极和栅极; 在源极上的第二层二硅化钴，所述第一层基本上不含有一氧化硅钴，并且所述第一层在其上基本上不具有钛氧化物的桁条; 漏极上的第二层二硅化锡，所述第二层基本上不具有在其上的钛氧化物基本上没有棱的钴单硅化物; 和在栅极上的第二层二硅化锡，所述第三层基本上不含有一氧化硅钴，并且在其上基本上没有钛氧化物的桁条。

    Implementing enhanced SRAM read performance sort ring oscillator (PSRO)
    9.
    发明授权
    Implementing enhanced SRAM read performance sort ring oscillator (PSRO) 有权
    实现增强型SRAM读取性能排序环形振荡器（PSRO）

    公开(公告)号：US07609542B2

    公开(公告)日：2009-10-27

    申请号：US11873534

    申请日：2007-10-17

    申请人： Chad Allen Adams ,  Todd Alan Christensen ,  Travis Reynold Hebig ,  Kirk David Peterson

    发明人： Chad Allen Adams ,  Todd Alan Christensen ,  Travis Reynold Hebig ,  Kirk David Peterson

    IPC分类号： G11C11/40

    CPC分类号： G11C11/413

    摘要： A method and apparatus including a static random access memory (SRAM) cell implement an enhanced SRAM read performance sort ring oscillator (PSRO), and a design structure on which the subject circuit resides is provided. A pair of parallel reverse polarity connected inverters defines a static latch or cross-coupled memory cell. The SRAM cell includes independent left and right wordlines providing a respective gate input to a pair of access transistors used to access to the memory cell. The SRAM cell includes a voltage supply connection to one side of the static latch. For example, a complement side of the static latch is connected to the voltage supply. A plurality of the SRAM cells is assembled together to form a SRAM base block. A plurality of the SRAM base blocks is connected together to form the SRAM read PSRO.

    摘要翻译： 一种包括静态随机存取存储器（SRAM）单元的方法和装置实现增强的SRAM读取性能排序环形振荡器（PSRO），以及设置有被摄体电路所在的设计结构。 一对并联反极性连接的反相器定义了静态锁存器或交叉耦合存储器单元。 SRAM单元包括独立的左和右字线，为用于访问存储单元的一对存取晶体管提供相应的栅极输入。 SRAM单元包括到静态锁存器的一侧的电压供应连接。 例如，静态锁存器的补码侧连接到电源。 多个SRAM单元组装在一起以形成SRAM基块。 多个SRAM基块被连接在一起以形成SRAM读取PSRO。