公开(公告)号：US06690072B2

公开(公告)日：2004-02-10

申请号：US10156782

申请日：2002-05-24

申请人： Cyril Cabral, Jr. ,  Roy A. Carruthers ,  Kevin K. Chan ,  Jack O. Chu ,  Guy Moshe Cohen ,  Steven J. Koester ,  Christian Lavoie ,  Ronnen A. Roy

发明人： Cyril Cabral, Jr. ,  Roy A. Carruthers ,  Kevin K. Chan ,  Jack O. Chu ,  Guy Moshe Cohen ,  Steven J. Koester ,  Christian Lavoie ,  Ronnen A. Roy

IPC分类号： H01L2904

CPC分类号： H01L29/41783 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/161 ,  H01L29/665 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method (and structure) of forming a vertically-self-aligned silicide contact to an underlying SiGe layer, includes forming a layer of silicon of a first predetermined thickness on the SiGe layer and forming a layer of metal on the silicon layer, where the metal layer has a second predetermined thickness. A thermal annealing process at a predetermined temperature then forms a silicide of the silicon and metal, where the predetermined temperature is chosen to substantially preclude penetration of the silicide into the underlying SiGe layer.

摘要翻译： 形成垂直自对准的硅化物接触到下面的SiGe层的方法（和结构）包括在SiGe层上形成第一预定厚度的硅层，并在硅层上形成一层金属，其中 金属层具有第二预定厚度。 然后在预定温度下的热退火工艺形成硅和金属的硅化物，其中选择预定温度以基本排除硅化物渗透到下面的SiGe层中。

公开(公告)号：US06972250B2

公开(公告)日：2005-12-06

申请号：US10419888

申请日：2003-04-22

申请人： Cyril Cabral, Jr. ,  Roy A. Carruthers ,  Kevin K. Chan ,  Jack O. Chu ,  Guy Moshe Cohen ,  Steven J. Koester ,  Christian Lavoie ,  Ronnen A. Roy

发明人： Cyril Cabral, Jr. ,  Roy A. Carruthers ,  Kevin K. Chan ,  Jack O. Chu ,  Guy Moshe Cohen ,  Steven J. Koester ,  Christian Lavoie ,  Ronnen A. Roy

IPC分类号： H01L21/285 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/161 ,  H01L21/4763

CPC分类号： H01L29/41783 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/161 ,  H01L29/665 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method (and structure) of forming a vertically-self-aligned silicide contact to an underlying SiGe layer, includes forming a layer of silicon of a first predetermined thickness on the SiGe layer and forming a layer of metal on the silicon layer, where the metal layer has a second predetermined thickness. A thermal annealing process at a predetermined temperature then forms a silicide of the silicon and metal, where the predetermined temperature is chosen to substantially preclude penetration of the silicide into the underlying SiGe layer.

摘要翻译： 形成垂直自对准的硅化物接触到下面的SiGe层的方法（和结构）包括在SiGe层上形成第一预定厚度的硅层，并在硅层上形成一层金属，其中 金属层具有第二预定厚度。 然后在预定温度下的热退火工艺形成硅和金属的硅化物，其中选择预定温度以基本排除硅化物渗入下面的SiGe层。

公开(公告)号：US07498640B2

公开(公告)日：2009-03-03

申请号：US10437930

申请日：2003-05-15

申请人： Cyril Cabral, Jr. ,  Kevin K. Chan ,  Guy Moshe Cohen ,  Kathryn Wilder Guarini ,  Christian Lavoie ,  Paul Michael Solomon ,  Ying Zhang

发明人： Cyril Cabral, Jr. ,  Kevin K. Chan ,  Guy Moshe Cohen ,  Kathryn Wilder Guarini ,  Christian Lavoie ,  Paul Michael Solomon ,  Ying Zhang

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/119 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L29/6653 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/41783 ,  H01L29/456 ,  H01L29/66507 ,  H01L29/66772 ,  H01L29/78618 ,  H01L29/78684 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method (and structure formed thereby) of forming a metal silicide contact on a non-planar silicon containing region having controlled consumption of the silicon containing region, includes forming a blanket metal layer over the silicon containing region, forming a silicon layer over the metal layer, etching anisotropically and selectively with respect to the metal the silicon layer, reacting the metal with silicon at a first temperature to form a metal silicon alloy, etching unreacted portions of the metal layer, annealing at a second temperature to form an alloy of metal-Si2, and selectively etching the unreacted silicon layer.

公开(公告)号：US06645861B2

公开(公告)日：2003-11-11

申请号：US09836197

申请日：2001-04-18

申请人： Cyril Cabral, Jr. ,  Kevin K. Chan ,  Guy Moshe Cohen ,  Kathryn Wilder Guarini ,  Christian Lavoie ,  Paul Michael Solomon ,  Ying Zhang

发明人： Cyril Cabral, Jr. ,  Kevin K. Chan ,  Guy Moshe Cohen ,  Kathryn Wilder Guarini ,  Christian Lavoie ,  Paul Michael Solomon ,  Ying Zhang

IPC分类号： H01L2144

CPC分类号： H01L29/6653 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/41783 ,  H01L29/456 ,  H01L29/66507 ,  H01L29/66772 ,  H01L29/78618 ,  H01L29/78684 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method (and structure formed thereby) of forming a metal silicide contact on a non-planar silicon containing region having controlled consumption of the silicon containing region, includes forming a blanket metal layer over the silicon containing region, forming a silicon layer over the metal layer, etching anisotropically and selectively with respect to the metal the silicon layer, reacting the metal with silicon at a first temperature to form a metal silicon alloy, etching unreacted portions of the metal layer, annealing at a second temperature to form an alloy of metal-Si2, and selectively etching the unreacted silicon layer.

摘要翻译： 在具有含硅区域的受控消耗的非平面含硅区域上形成金属硅化物接触的方法（以及由此形成的结构）包括在含硅区域上形成覆盖金属层，在金属上形成硅层 层，相对于金属的硅层各向异性地选择性地蚀刻，在第一温度下使金属与硅反应以形成金属硅合金，蚀刻金属层的未反应部分，在第二温度退火以形成金属合金 -Si2，并且选择性地蚀刻未反应的硅层。

公开(公告)号：US5634973A

公开(公告)日：1997-06-03

申请号：US587029

申请日：1996-01-16

申请人： Cyril Cabral, Jr. ,  Kevin K. Chan ,  Jack O. Chu ,  James M. E. Harper

发明人： Cyril Cabral, Jr. ,  Kevin K. Chan ,  Jack O. Chu ,  James M. E. Harper

IPC分类号： C30B29/06 ,  C23C14/08 ,  C23C16/04 ,  H01L21/20 ,  H01L21/203 ,  H01L21/205 ,  C30B33/06

CPC分类号： H01L21/02642 ,  H01L21/02373 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02631 ,  Y10S148/106 ,  Y10S438/945

摘要： Epitaxial and polycrystalline layers of silicon and silicon-germanium alloys are selectively grown on a semiconductor substrate or wafer by forming over the wafer a thin film masking layer of an oxide of an element selected from scandium, yttrium, lanthanum, cerium, praseodymium, neodymium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium; and then growing the epitaxial layer over the wafer at temperatures below 650.degree. C. The epitaxial and polycrystalline layers do not grow on the masking layer. The invention overcomes the problem of forming epitaxial layers at temperatures above 650.degree. C. by providing a lower temperature process.

摘要翻译： 通过在晶片上形成选自钪，钇，镧，铈，镨，钕，钕，钕等的元素的氧化物的薄膜掩蔽层，选择性地在半导体衬底或晶片上生长硅和硅 - 锗合金的外延和多晶层， 钐，铕，钆，铽，镝，钬，铒，ium，镱和镥; 然后在低于650℃的温度下在晶片上生长外延层。外延层和多晶层不会在掩模层上生长。 本发明克服了通过提供较低温度的工艺在高于650℃的温度下形成外延层的问题。

公开(公告)号：US5595600A

公开(公告)日：1997-01-21

申请号：US469650

申请日：1995-06-06

申请人： Cyril Cabral, Jr. ,  Kevin K. Chan ,  Jack O. Chu ,  James M. E. Harper

发明人： Cyril Cabral, Jr. ,  Kevin K. Chan ,  Jack O. Chu ,  James M. E. Harper

IPC分类号： C30B29/06 ,  C23C14/08 ,  C23C16/04 ,  H01L21/20 ,  H01L21/203 ,  H01L21/205

CPC分类号： H01L21/02642 ,  H01L21/02373 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02631 ,  Y10S148/106 ,  Y10S438/945

摘要： Epitaxial and polycrystalline layers of silicon and silicon-germanium alloys are selectively grown on a semiconductor substrate or wafer by forming over the wafer a thin film masking layer of an oxide of an element selected from scandium, yttrium, lanthanum, cerium, praseodymium, neodymium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium; and then growing the epitaxial layer over the wafer at temperatures below 650.degree. C. The epitaxial and polycrystalline layers do not grow on the masking layer. The invention overcomes the problem of forming epitaxial layers at temperatures above 650.degree. C. by providing a lower temperature process.

公开(公告)号：US5565031A

公开(公告)日：1996-10-15

申请号：US390132

申请日：1995-02-17

申请人： Cyril Cabral, Jr. ,  Kevin K. Chan ,  Jack O. Chu ,  James M. E. Harper

发明人： Cyril Cabral, Jr. ,  Kevin K. Chan ,  Jack O. Chu ,  James M. E. Harper

IPC分类号： C30B29/06 ,  C23C14/08 ,  C23C16/04 ,  H01L21/20 ,  H01L21/203 ,  H01L21/205

CPC分类号： H01L21/02642 ,  H01L21/02373 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02631 ,  Y10S148/106 ,  Y10S438/945

摘要： Epitaxial and polycrystalline layers of silicon and silicon-germanium alloys are selectively grown on a semiconductor substrate or wafer by forming over the wafer a thin film masking layer of an oxide of an element selected from scandium, yttrium, lanthanum, cerium, praseodymium, neodymium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium; and then growing the epitaxial layer over the wafer at temperatures below 650.degree. C. The epitaxial and polycrystalline layers do not grow on the masking layer. The invention overcomes the problem of forming epitaxial layers at temperatures above 650.degree. C. by providing a lower temperature process.

摘要翻译： 通过在晶片上形成选自钪，钇，镧，铈，镨，钕，钕，钕等的元素的氧化物的薄膜掩蔽层，选择性地在半导体衬底或晶片上生长硅和硅 - 锗合金的外延和多晶层， 钐，铕，钆，铽，镝，钬，铒，ium，镱和镥; 然后在低于650℃的温度下在晶片上生长外延层。外延层和多晶层不会在掩模层上生长。 本发明克服了通过提供较低温度的工艺在高于650℃的温度下形成外延层的问题。

公开(公告)号：US5427630A

公开(公告)日：1995-06-27

申请号：US240060

申请日：1994-05-09

申请人： Cyril Cabral, Jr. ,  Kevin K. Chan ,  Jack O. Chu ,  James M. E. Harper

发明人： Cyril Cabral, Jr. ,  Kevin K. Chan ,  Jack O. Chu ,  James M. E. Harper

IPC分类号： C30B29/06 ,  C23C14/08 ,  C23C16/04 ,  H01L21/20 ,  H01L21/203 ,  H01L21/205 ,  H01R21/22

CPC分类号： H01L21/02642 ,  H01L21/02373 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02631 ,  Y10S148/106 ,  Y10S438/945

摘要： Epitaxial and polycrystalline layers of silicon and silicon-germanium alloys are selectively grown on a semiconductor substrate or wafer by forming over the wafer a thin film masking layer of an oxide of element selected from scandium, yttrium, lanthanum, cerium, praseodymium, neodymium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium and then growing the epitaxial layer over the wafer at temperatures below 650.degree. C. The epitaxial and polycrystalline layers do not grow on the masking layer. The invention overcomes the problem of forming epitaxial layers at temperatures above 650.degree. C. by providing a lower temperature process.

摘要翻译： 通过在晶片上形成选自钪，钇，镧，铈，镨，钕，钐的元素氧化物的薄膜掩蔽层，在半导体衬底或晶片上选择性地生长硅和硅 - 锗合金的外延和多晶层 ，铕，钆，铽，镝，钬，铒，ium，镱和镥，然后在低于650℃的温度下在晶片上生长外延层。外延和多晶层不会在掩模层上生长。 本发明克服了通过提供较低温度的工艺在高于650℃的温度下形成外延层的问题。

公开(公告)号：US06448131B1

公开(公告)日：2002-09-10

申请号：US09929182

申请日：2001-08-14

申请人： Cyril Cabral, Jr. ,  Kevin K. Chan ,  Guy M. Cohen ,  Ramachandra Divakaruni ,  Christian Lavoie ,  Fenton R. McFeely

发明人： Cyril Cabral, Jr. ,  Kevin K. Chan ,  Guy M. Cohen ,  Ramachandra Divakaruni ,  Christian Lavoie ,  Fenton R. McFeely

IPC分类号： H01L218242

CPC分类号： H01L27/1087 ,  H01L28/84 ,  H01L29/66181 ,  Y10S438/964

摘要： A method for increasing the trench capacitor surface area is provided. The method, which utilizes a metal silicide to roughen the trench walls, increases capacitance due to the increase in the trench surface area after the silicide has been removed. The roughening of the trench walls can be controlled by varying one or more of the following parameters: the density of the metal, the metal film thickness, the silicide phase, and the choice of the metal. Once the metal is deposited in the trench, the method is self-limited. Shrinking the trench to its original width can be obtained by subsequent silicon deposition or by diffusion of silicon from a cap layer through the silicide.

摘要翻译： 提供了一种用于增加沟槽电容器表面积的方法。 利用金属硅化物粗糙化沟槽壁的方法由于硅化物被去除之后的沟槽表面积的增加而增加了电容。 可以通过改变一个或多个以下参数来控制沟槽壁的粗糙化：金属的密度，金属膜厚度，硅化物相以及金属的选择。 一旦金属沉积在沟槽中，该方法是自限制的。 通过随后的硅沉积或通过硅化物从盖层扩散硅可以获得将沟槽缩小至原始宽度。

公开(公告)号：US06444578B1

公开(公告)日：2002-09-03

申请号：US09791024

申请日：2001-02-21

申请人： Cyril Cabral, Jr. ,  Roy Arthur Carruthers ,  Kevin K. Chan ,  Guy M. Cohen ,  Kathryn Wilder Guarini ,  James M. Harper ,  Christian Lavoie ,  Paul M. Solomon

发明人： Cyril Cabral, Jr. ,  Roy Arthur Carruthers ,  Kevin K. Chan ,  Guy M. Cohen ,  Kathryn Wilder Guarini ,  James M. Harper ,  Christian Lavoie ,  Paul M. Solomon

IPC分类号： H01L2144

CPC分类号： H01L21/28518

摘要： The present invention relates to a method of reducing Si consumption during a self-aligned silicide process which employs a M—Si or M—Si—Ge alloy, where M is Co, Ni or CoNi and a blanket layer of Si. The present invention is particularly useful in minimizing Si consumption in shallow junction and thin silicon-on-insulator (SOI) electronic devices.

摘要翻译： 本发明涉及在采用M-Si或M-Si-Ge合金的自对准硅化物工艺中降低Si消耗的方法，其中M是Co，Ni或CoNi以及Si的覆盖层。 本发明特别可用于最大限度地减少浅结和薄绝缘体上硅（SOI）电子器件中的Si消耗。