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公开(公告)号：US11526463B2
公开(公告)日：2022-12-13
申请号：US17355458
申请日：2021-06-23
Applicant: D-WAVE SYSTEMS INC.
Inventor： Alexander Maassen van den Brink , Peter Love , Mohammad H. S. Amin , Geordie Rose , David Grant , Miles F. H. Steininger , Paul I. Bunyk , Andrew J. Berkley
Abstract: Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices.
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公开(公告)号：US20200293486A1
公开(公告)日：2020-09-17
申请号：US16859672
申请日：2020-04-27
Applicant: D-WAVE SYSTEMS INC.
Inventor： Alexander Maassen van den Brink , Peter Love , Mohammad H.S. Amin , Geordie Rose , David Grant , Miles F.H. Steininger , Paul I. Bunyk , Andrew J. Berkley
Abstract: Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices.
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公开(公告)号：US20190324941A1
公开(公告)日：2019-10-24
申请号：US16421211
申请日：2019-05-23
Applicant: D-WAVE SYSTEMS INC.
Inventor： Alexander Maassen van den Brink , Peter Love , Mohammad H.S. Amin , Geordie Rose , David Grant , Miles F.H. Steininger , Paul I. Bunyk , Andrew J. Berkley
Abstract: Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices.
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公开(公告)号：US20170177751A1
公开(公告)日：2017-06-22
申请号：US15419083
申请日：2017-01-30
Applicant: D-Wave Systems Inc.
Inventor： William G. Macready , Geordie Rose , Thomas F.W. Mahon , Peter Love , Marshall Drew-Brook
CPC classification number: G06F17/505 , B82Y10/00 , G06F17/11 , G06N99/002
Abstract: Solving computational problems may include generating a logic circuit representation of the computational problem, encoding the logic circuit representation as a discrete optimization problem, and solving the discrete optimization problem using a quantum processor. Output(s) of the logic circuit representation may be clamped such that the solving involves effectively executing the logic circuit representation in reverse to determine input(s) that corresponds to the clamped output(s). The representation may be of a Boolean logic circuit. The discrete optimization problem may be composed of a set of miniature optimization problems, where each miniature optimization problem encodes a respective logic gate from the logic circuit representation. A quantum processor may include multiple sets of qubits, each set coupled to respective annealing signal lines such that dynamic evolution of each set of qubits is controlled independently from the dynamic evolutions of the other sets of qubits.
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公开(公告)号：US20190087385A1
公开(公告)日：2019-03-21
申请号：US16173846
申请日：2018-10-29
Applicant: D-WAVE SYSTEMS INC.
Inventor： Alexander Maassen van den Brink , Peter Love , Mohammad H.S. Amin , Geordie Rose , David Grant , Miles F. H. Steininger , Paul I. Bunyk , Andrew J. Berkley
Abstract: Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices.
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Patent Agency Ranking
公开(公告)号：US09665539B1
公开(公告)日：2017-05-30
申请号：US15419083
申请日：2017-01-30
Applicant: D-Wave Systems Inc.
Inventor： William G. Macready , Geordie Rose , Thomas F.W. Mahon , Peter Love , Marshall Drew-Brook
CPC classification number: G06F17/505 , B82Y10/00 , G06F17/11 , G06N99/002
Abstract: Solving computational problems may include generating a logic circuit representation of the computational problem, encoding the logic circuit representation as a discrete optimization problem, and solving the discrete optimization problem using a quantum processor. Output(s) of the logic circuit representation may be clamped such that the solving involves effectively executing the logic circuit representation in reverse to determine input(s) that corresponds to the clamped output(s). The representation may be of a Boolean logic circuit. The discrete optimization problem may be composed of a set of miniature optimization problems, where each miniature optimization problem encodes a respective logic gate from the logic circuit representation. A quantum processor may include multiple sets of qubits, each set coupled to respective annealing signal lines such that dynamic evolution of each set of qubits is controlled independently from the dynamic evolutions of the other sets of qubits.
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公开(公告)号：US09594726B2
公开(公告)日：2017-03-14
申请号：US15190608
申请日：2016-06-23
Applicant: D-Wave Systems Inc.
Inventor： William G. Macready , Geordie Rose , Thomas F. W. Mahon , Peter Love , Marshall Drew-Brook
CPC classification number: G06F17/505 , B82Y10/00 , G06F17/11 , G06N99/002
Abstract: Solving computational problems may include generating a logic circuit representation of the computational problem, encoding the logic circuit representation as a discrete optimization problem, and solving the discrete optimization problem using a quantum processor. Output(s) of the logic circuit representation may be clamped such that the solving involves effectively executing the logic circuit representation in reverse to determine input(s) that corresponds to the clamped output(s). The representation may be of a Boolean logic circuit. The discrete optimization problem may be composed of a set of miniature optimization problems, where each miniature optimization problem encodes a respective logic gate from the logic circuit representation. A quantum processor may include multiple sets of qubits, each set coupled to respective annealing signal lines such that dynamic evolution of each set of qubits is controlled independently from the dynamic evolutions of the other sets of qubits.
Abstract translation: 解决计算问题可能包括生成计算问题的逻辑电路表示，将逻辑电路表示编码为离散优化问题，以及使用量子处理器来解决离散优化问题。 可以钳位逻辑电路表示的输出，使得解决方案涉及有效地执行逻辑电路表示，以确定对应于被钳位的输出的输入。 该表示可以是布尔逻辑电路。 离散优化问题可以由一组微型优化问题组成，其中每个微型优化问题从逻辑电路表示编码相应的逻辑门。 量子处理器可以包括多组量子位，每组量子位耦合到相应的退火信号线，使得每组量子位的动态演化独立于其他量子位集合的动态演化被控制。
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公开(公告)号：US20160371227A1
公开(公告)日：2016-12-22
申请号：US15190608
申请日：2016-06-23
Applicant: D-Wave Systems Inc.
Inventor： William G. Macready , Geordie Rose , Thomas F.W. Mahon , Peter Love , Marshall Drew-Brook
CPC classification number: G06F17/505 , B82Y10/00 , G06F17/11 , G06N99/002
Abstract: Solving computational problems may include generating a logic circuit representation of the computational problem, encoding the logic circuit representation as a discrete optimization problem, and solving the discrete optimization problem using a quantum processor. Output(s) of the logic circuit representation may be clamped such that the solving involves effectively executing the logic circuit representation in reverse to determine input(s) that corresponds to the clamped output(s). The representation may be of a Boolean logic circuit. The discrete optimization problem may be composed of a set of miniature optimization problems, where each miniature optimization problem encodes a respective logic gate from the logic circuit representation. A quantum processor may include multiple sets of qubits, each set coupled to respective annealing signal lines such that dynamic evolution of each set of qubits is controlled independently from the dynamic evolutions of the other sets of qubits.
Abstract translation: 解决计算问题可能包括生成计算问题的逻辑电路表示，将逻辑电路表示编码为离散优化问题，以及使用量子处理器来解决离散优化问题。 可以钳位逻辑电路表示的输出，使得解决方案涉及有效执行逻辑电路表示，以确定对应于被钳位的输出的输入。 该表示可以是布尔逻辑电路。 离散优化问题可以由一组微型优化问题组成，其中每个微型优化问题从逻辑电路表示编码相应的逻辑门。 量子处理器可以包括多组量子位，每组量子位耦合到相应的退火信号线，使得每组量子位的动态演化独立于其他量子位集合的动态演化被控制。
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公开(公告)号：US20140245249A1
公开(公告)日：2014-08-28
申请号：US14186895
申请日：2014-02-21
Applicant: D-Wave Systems Inc.
Inventor： William Macready , Geordie Rose , Thomas Mahon , Peter Love , Marshall Drew-Brook
IPC: G06F17/50
CPC classification number: G06F17/505 , B82Y10/00 , G06F17/11 , G06N99/002
Abstract: Solving computational problems may include generating a logic circuit representation of the computational problem, encoding the logic circuit representation as a discrete optimization problem, and solving the discrete optimization problem using a quantum processor. Output(s) of the logic circuit representation may be clamped such that the solving involves effectively executing the logic circuit representation in reverse to determine input(s) that corresponds to the clamped output(s). The representation may be of a Boolean logic circuit. The discrete optimization problem may be composed of a set of miniature optimization problems, where each miniature optimization problem encodes a respective logic gate from the logic circuit representation. A quantum processor may include multiple sets of qubits, each set coupled to respective annealing signal lines such that dynamic evolution of each set of qubits is controlled independently from the dynamic evolutions of the other sets of qubits.
Abstract translation: 解决计算问题可能包括生成计算问题的逻辑电路表示，将逻辑电路表示编码为离散优化问题，以及使用量子处理器求解离散优化问题。 可以钳位逻辑电路表示的输出，使得解决方案涉及有效地执行逻辑电路表示，以确定对应于被钳位的输出的输入。 该表示可以是布尔逻辑电路。 离散优化问题可以由一组微型优化问题组成，其中每个微型优化问题从逻辑电路表示编码相应的逻辑门。 量子处理器可以包括多组量子位，每组量子位耦合到相应的退火信号线，使得每组量子位的动态演化独立于其他量子位集合的动态演化被控制。
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公开(公告)号：US20130144925A1
公开(公告)日：2013-06-06
申请号：US13678266
申请日：2012-11-15
Applicant: D-Wave Systems Inc.
Inventor： William Macready , Geordie Rose , Thomas Mahon , Peter Love , Marshall Drew-Brook
IPC: G06F17/10
CPC classification number: G06F17/10 , B82Y10/00 , G06F17/11 , G06N99/002
Abstract: Solving computational problems may include generating a logic circuit representation of the computational problem, encoding the logic circuit representation as a discrete optimization problem, and solving the discrete optimization problem using a quantum processor. Output(s) of the logic circuit representation may be clamped such that the solving involves effectively executing the logic circuit representation in reverse to determine input(s) that corresponds to the clamped output(s). The representation may be of a multiplication circuit. The discrete optimization problem may be composed of a set of miniature optimization problems, where each miniature optimization problem encodes a respective logic gate from the logic circuit representation. A multiplication circuit may employ binary representations of factors, and these binary representations may be decomposed to reduce the total number of variables required to represent the multiplication circuit.
Abstract translation: 解决计算问题可能包括生成计算问题的逻辑电路表示，将逻辑电路表示编码为离散优化问题，以及使用量子处理器来解决离散优化问题。 可以钳位逻辑电路表示的输出，使得解决方案涉及有效地执行逻辑电路表示，以确定对应于被钳位的输出的输入。 该表示可以是乘法电路。 离散优化问题可以由一组微型优化问题组成，其中每个微型优化问题从逻辑电路表示编码相应的逻辑门。 乘法电路可以采用因子的二进制表示，并且这些二进制表示可以被分解以减少表示乘法电路所需的变量的总数。
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