公开(公告)号：US20120086077A1

公开(公告)日：2012-04-12

申请号：US12899635

申请日：2010-10-07

申请人： DAVID M FRIED ,  Jeffrey B. Johnson ,  Kevin McStay ,  Paul C. Parries ,  Chengwen Pei ,  Gan Wang ,  Geng Wang ,  Yanli Zhang

发明人： DAVID M FRIED ,  Jeffrey B. Johnson ,  Kevin McStay ,  Paul C. Parries ,  Chengwen Pei ,  Gan Wang ,  Geng Wang ,  Yanli Zhang

IPC分类号： H01L29/06 ,  H01L21/336

CPC分类号： H01L29/0847 ,  H01L21/26586 ,  H01L27/1203 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7833

摘要： An FET structure on a semiconductor substrate which includes forming recesses for a source and a drain of the gate structure on a semiconductor substrate, halo implanting regions through the bottom of the source and drain recesses, the halo implanted regions being underneath the gate stack, implanting junction butting at the bottom of the source and drain recesses, and filling the source and drain recesses with a doped epitaxial material. In exemplary embodiments, the semiconductor substrate is a semiconductor on insulator substrate including a semiconductor layer on a buried oxide layer. In exemplary embodiments, the junction butting and halo implanted regions are in contact with the buried oxide layer. In other exemplary embodiments, there is no junction butting. In exemplary embodiments, halo implants implanted to a lower part of the FET body underneath the gate structure provide higher doping level in lower part of the FET body to reduce body resistance, without interfering with FET threshold voltage.

摘要翻译： 半导体衬底上的FET结构，其包括在半导体衬底上形成用于栅极结构的源极和漏极的凹槽，通过源极和漏极凹部的底部的晕圈注入区域，位于栅极叠层下方的晕圈注入区域，注入 在源极和漏极凹部的底部接合，并且用掺杂的外延材料填充源极和漏极凹部。 在示例性实施例中，半导体衬底是在掩埋氧化物层上包括半导体层的绝缘体上半导体衬底。 在示例性实施例中，接合对接和晕圈注入区域与掩埋氧化物层接触。 在其他示例性实施例中，没有接合对接。 在示例性实施例中，注入到栅极结构下面的FET体的下部的卤素注入在FET体的下部提供更高的掺杂水平，以降低体电阻，而不会干扰FET阈值电压。

公开(公告)号：US08236632B2

公开(公告)日：2012-08-07

申请号：US12899635

申请日：2010-10-07

申请人： David M. Fried ,  Jeffrey B. Johnson ,  Kevin McStay ,  Paul C. Parries ,  Chengwen Pei ,  Gan Wang ,  Geng Wang ,  Yanli Zhang

发明人： David M. Fried ,  Jeffrey B. Johnson ,  Kevin McStay ,  Paul C. Parries ,  Chengwen Pei ,  Gan Wang ,  Geng Wang ,  Yanli Zhang

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L21/338

CPC分类号： H01L29/0847 ,  H01L21/26586 ,  H01L27/1203 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7833

摘要： An FET structure on a semiconductor substrate which includes forming recesses for a source and a drain of the gate structure on a semiconductor substrate, halo implanting regions through the bottom of the source and drain recesses, the halo implanted regions being underneath the gate stack, implanting junction butting at the bottom of the source and drain recesses, and filling the source and drain recesses with a doped epitaxial material. In exemplary embodiments, the semiconductor substrate is a semiconductor on insulator substrate including a semiconductor layer on a buried oxide layer. In exemplary embodiments, the junction butting and halo implanted regions are in contact with the buried oxide layer. In other exemplary embodiments, there is no junction butting. In exemplary embodiments, halo implants implanted to a lower part of the FET body underneath the gate structure provide higher doping level in lower part of the FET body to reduce body resistance, without interfering with FET threshold voltage.

摘要翻译： 半导体衬底上的FET结构，其包括在半导体衬底上形成用于栅极结构的源极和漏极的凹槽，通过源极和漏极凹部的底部的晕圈注入区域，位于栅极叠层下方的晕圈注入区域，注入 在源极和漏极凹部的底部接合，并且用掺杂的外延材料填充源极和漏极凹部。 在示例性实施例中，半导体衬底是在掩埋氧化物层上包括半导体层的绝缘体上半导体衬底。 在示例性实施例中，接合对接和晕圈注入区域与掩埋氧化物层接触。 在其他示例性实施例中，没有接合对接。 在示例性实施例中，注入到栅极结构下面的FET体的下部的卤素注入在FET体的下部提供更高的掺杂水平，以降低体电阻，而不会干扰FET阈值电压。

公开(公告)号：US20120187490A1

公开(公告)日：2012-07-26

申请号：US13426547

申请日：2012-03-21

申请人： David M. Fried ,  Jeffrey B. Johnson ,  Kevin McStay ,  Paul C. Parries ,  Chengwen Pei ,  Gan Wang ,  Geng Wang ,  Yanli Zhang

发明人： David M. Fried ,  Jeffrey B. Johnson ,  Kevin McStay ,  Paul C. Parries ,  Chengwen Pei ,  Gan Wang ,  Geng Wang ,  Yanli Zhang

IPC分类号： H01L29/78

CPC分类号： H01L29/0847 ,  H01L21/26586 ,  H01L27/1203 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7833

摘要： A field effect transistor (FET) structure on a semiconductor substrate which includes a gate structure having a spacer on a semiconductor substrate; an extension implant underneath the gate structure; a recessed source and a recessed drain filled with a doped epitaxial material; halo implanted regions adjacent a bottom of the recessed source and drain and being underneath the gate stack. In an exemplary embodiment, there is implanted junction butting underneath the bottom of each of the recessed source and drain, the junction butting being separate and distinct from the halo implanted regions. In another exemplary embodiment, the doped epitaxial material is graded from a lower dopant concentration at a side of the recessed source and drain to a higher dopant concentration at a center of the recessed source and drain. In a further exemplary embodiment, the semiconductor substrate is a semiconductor on insulator substrate.

摘要翻译： 一种半导体衬底上的场效应晶体管（FET）结构，其包括在半导体衬底上具有间隔物的栅极结构; 栅极结构下面的延伸植入物; 凹陷的源极和填充有掺杂的外延材料的凹陷的漏极; 邻近凹陷源的底部的卤素注入区域和漏极并位于栅极叠层下方。 在示例性实施例中，在凹陷源和漏极中的每一个的底部下方注入结合对接，该接合部分与光晕注入区域分开且不同。 在另一个示例性实施例中，掺杂的外延材料从凹陷源的一侧的较低掺杂剂浓度和漏极分级到凹陷源极和漏极的中心处的较高掺杂剂浓度。 在另一示例性实施例中，半导体衬底是绝缘体上半导体衬底。

公开(公告)号：US08809953B2

公开(公告)日：2014-08-19

申请号：US13426547

申请日：2012-03-21

申请人： David M. Fried ,  Jeffrey B. Johnson ,  Kevin McStay ,  Paul Parries ,  Chengwen Pei ,  Gan Wang ,  Geng Wang ,  Yanli Zhang

发明人： David M. Fried ,  Jeffrey B. Johnson ,  Kevin McStay ,  Paul Parries ,  Chengwen Pei ,  Gan Wang ,  Geng Wang ,  Yanli Zhang

IPC分类号： H01L29/78

CPC分类号： H01L29/0847 ,  H01L21/26586 ,  H01L27/1203 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7833

摘要： A field effect transistor (FET) structure on a semiconductor substrate which includes a gate structure having a spacer on a semiconductor substrate; an extension implant underneath the gate structure; a recessed source and a recessed drain filled with a doped epitaxial material; halo implanted regions adjacent a bottom of the recessed source and drain and being underneath the gate stack. In an exemplary embodiment, there is implanted junction butting underneath the bottom of each of the recessed source and drain, the junction butting being separate and distinct from the halo implanted regions. In another exemplary embodiment, the doped epitaxial material is graded from a lower dopant concentration at a side of the recessed source and drain to a higher dopant concentration at a center of the recessed source and drain. In a further exemplary embodiment, the semiconductor substrate is a semiconductor on insulator substrate.

摘要翻译： 一种半导体衬底上的场效应晶体管（FET）结构，其包括在半导体衬底上具有间隔物的栅极结构; 栅极结构下面的延伸植入物; 凹陷的源极和填充有掺杂的外延材料的凹陷的漏极; 邻近凹陷源的底部的卤素注入区域和漏极并位于栅极叠层下方。 在示例性实施例中，在凹陷源和漏极中的每一个的底部下方注入结合对接，该接合部分与光晕注入区域分开且不同。 在另一个示例性实施例中，掺杂的外延材料从凹陷源的一侧的较低掺杂剂浓度和漏极分级到凹陷源极和漏极的中心处的较高掺杂剂浓度。 在另一示例性实施例中，半导体衬底是绝缘体上半导体衬底。

公开(公告)号：US09484269B2

公开(公告)日：2016-11-01

申请号：US12822492

申请日：2010-06-24

申请人： Joseph Ervin ,  Jeffrey B. Johnson ,  Kevin McStay ,  Paul C. Parries ,  Chengwen Pei ,  Geng Wang ,  Yanli Zhang

发明人： Joseph Ervin ,  Jeffrey B. Johnson ,  Kevin McStay ,  Paul C. Parries ,  Chengwen Pei ,  Geng Wang ,  Yanli Zhang

IPC分类号： H01L27/12 ,  H01L21/8242 ,  H01L21/84 ,  H01L21/762 ,  H01L27/108

CPC分类号： H01L21/84 ,  H01L21/76237 ,  H01L27/10847 ,  H01L27/1203

摘要： Semiconductor structures and methods to control bottom corner threshold in a silicon-on-insulator (SOI) device. A method includes doping a corner region of a semiconductor-on-insulator (SOI) island. The doping includes tailoring a localized doping of the corner region to reduce capacitive coupling of the SOI island with an adjacent structure.

摘要翻译： 半导体结构和方法来控制绝缘体上硅（SOI）器件中的底角阈值。 一种方法包括掺杂绝缘体上半导体（SOI）岛的角区域。 掺杂包括定制角区域的局部掺杂以减少SOI岛与相邻结构的电容耦合。

公开(公告)号：US08395217B1

公开(公告)日：2013-03-12

申请号：US13283031

申请日：2011-10-27

申请人： Kangguo Cheng ,  Joseph Ervin ,  Jeffrey B. Johnson ,  Pranita Kulkarni ,  Kevin McStay ,  Paul C. Parries ,  Chengwen Pei ,  Geng Wang ,  Yanli Zhang

发明人： Kangguo Cheng ,  Joseph Ervin ,  Jeffrey B. Johnson ,  Pranita Kulkarni ,  Kevin McStay ,  Paul C. Parries ,  Chengwen Pei ,  Geng Wang ,  Yanli Zhang

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L21/84 ,  H01L21/76289 ,  H01L21/823878 ,  H01L27/1203

摘要： A semiconductor device structure having an isolation region and method of manufacturing the same are provided. The semiconductor device structure includes a silicon-on-insulator (SOI) substrate. A plurality of gates is formed on the SOI substrate. The semiconductor device structure further includes trenches having sidewalls, formed between each of the plurality of gates. The semiconductor device structure further includes an epitaxial lateral growth layer formed in the trenches. The epitaxial lateral growth layer is grown laterally from the opposing sidewalls of the trenches, so that the epitaxial lateral growth layer encloses a portion of the trenches extended into the SOI substrate. The epitaxial lateral growth layer is formed in such way that it includes an air gap region overlying a buried dielectric layer of the SOI substrate.

摘要翻译： 提供了具有隔离区域的半导体器件结构及其制造方法。 半导体器件结构包括绝缘体上硅（SOI）衬底。 在SOI衬底上形成多个栅极。 半导体器件结构还包括形成在多个栅极中的每一个之间的具有侧壁的沟槽。 半导体器件结构还包括形成在沟槽中的外延横向生长层。 外延横向生长层从沟槽的相对侧壁横向生长，使得外延横向生长层包围延伸到SOI衬底中的沟槽的一部分。 外延横向生长层以这样的方式形成，使得其包括覆盖SOI衬底的掩埋介电层的气隙区域。

公开(公告)号：US07989298B1

公开(公告)日：2011-08-02

申请号：US12692859

申请日：2010-01-25

申请人： Kevin K. Chan ,  Brian J. Greene ,  Judson R. Holt ,  Jeffrey B. Johnson ,  Thomas S. Kanarsky ,  Jophy S. Koshy ,  Kevin McStay ,  Dae-Gyu Park ,  Johan W. Weijtmans ,  Frank B. Yang

发明人： Kevin K. Chan ,  Brian J. Greene ,  Judson R. Holt ,  Jeffrey B. Johnson ,  Thomas S. Kanarsky ,  Jophy S. Koshy ,  Kevin McStay ,  Dae-Gyu Park ,  Johan W. Weijtmans ,  Frank B. Yang

IPC分类号： H01L21/336 ,  H01L21/76

CPC分类号： H01L29/165 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A semiconductor device and a method of making the device are provided. The method can include forming a gate conductor overlying a major surface of a monocrystalline semiconductor region and forming first spacers on exposed walls of the gate conductor. Using the gate conductor and the first spacers as a mask, at least extension regions are implanted in the semiconductor region and dummy spacers are formed extending outward from the first spacers. Using the dummy spacers as a mask, the semiconductor region is etched to form recesses having at least substantially straight walls extending downward from the major surface to a bottom surface, such that a substantial angle is defined between the bottom surface and the walls. Subsequently, the process is continued by epitaxially growing regions of stressed monocrystalline semiconductor material within the recesses. Then the dummy spacers are removed and the transistor can be completed by forming source/drain regions of the transistor that are at least partially disposed in the stressed semiconductor material regions.

摘要翻译： 提供半导体器件和制造该器件的方法。 该方法可以包括形成覆盖在单晶半导体区域的主表面上的栅极导体并且在栅极导体的暴露的壁上形成第一间隔物。 使用栅极导体和第一间隔物作为掩模，至少延伸区域注入到半导体区域中，并且形成从第一间隔物向外延伸的虚设间隔物。 使用虚拟间隔件作为掩模，半导体区域被蚀刻以形成具有从主表面向底表面向下延伸的至少基本上直的壁的凹槽，使得在底表面和壁之间限定大的角度。 随后，通过在凹槽内外延生长应力单晶半导体材料的区域来继续该过程。 然后去除虚拟间隔物，并且可以通过形成至少部分地设置在受应力的半导体材料区域中的晶体管的源极/漏极区域来完成晶体管。

公开(公告)号：US20110183486A1

公开(公告)日：2011-07-28

申请号：US12692859

申请日：2010-01-25

申请人： Kevin K. Chan ,  Brian J. Greene ,  Judson R. Holt ,  Jeffrey B. Johnson ,  Thomas S. Kanarsky ,  Jophy S. Koshy ,  Kevin McStay ,  Dae-Gyu Park ,  Johan W. Weijtmans ,  Frank B. Yang

发明人： Kevin K. Chan ,  Brian J. Greene ,  Judson R. Holt ,  Jeffrey B. Johnson ,  Thomas S. Kanarsky ,  Jophy S. Koshy ,  Kevin McStay ,  Dae-Gyu Park ,  Johan W. Weijtmans ,  Frank B. Yang

IPC分类号： H01L21/336

CPC分类号： H01L29/165 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A semiconductor device and a method of making the device are provided. The method can include forming a gate conductor overlying a major surface of a monocrystalline semiconductor region and forming first spacers on exposed walls of the gate conductor. Using the gate conductor and the first spacers as a mask, at least extension regions are implanted in the semiconductor region and dummy spacers are formed extending outward from the first spacers. Using the dummy spacers as a mask, the semiconductor region is etched to form recesses having at least substantially straight walls extending downward from the major surface to a bottom surface, such that a substantial angle is defined between the bottom surface and the walls. Subsequently, the process is continued by epitaxially growing regions of stressed monocrystalline semiconductor material within the recesses. Then the dummy spacers are removed and the transistor can be completed by forming source/drain regions of the transistor that are at least partially disposed in the stressed semiconductor material regions.

摘要翻译： 提供半导体器件和制造该器件的方法。 该方法可以包括形成覆盖在单晶半导体区域的主表面上的栅极导体并且在栅极导体的暴露的壁上形成第一间隔物。 使用栅极导体和第一间隔物作为掩模，至少延伸区域注入到半导体区域中，并且形成从第一间隔物向外延伸的虚设间隔物。 使用虚拟间隔件作为掩模，半导体区域被蚀刻以形成具有从主表面向底表面向下延伸的至少基本上直的壁的凹槽，使得在底表面和壁之间限定大的角度。 随后，通过在凹槽内外延生长应力单晶半导体材料的区域来继续该过程。 然后去除虚拟间隔物，并且可以通过形成至少部分地设置在受应力的半导体材料区域中的晶体管的源极/漏极区域来完成晶体管。

公开(公告)号：US20050037561A1

公开(公告)日：2005-02-17

申请号：US10604731

申请日：2003-08-13

申请人： Geng Wang ,  Kevin McStay ,  Mary Weybright ,  Yujun Li ,  Dureseti Chidambarrao

发明人： Geng Wang ,  Kevin McStay ,  Mary Weybright ,  Yujun Li ,  Dureseti Chidambarrao

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/8242

CPC分类号： H01L27/10876 ,  H01L21/26586 ,  H01L27/10864 ,  H01L29/1041 ,  H01L29/66537 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/945

摘要： A method of formation of a deep trench vertical transistor is provided. A deep trench with a sidewall in a doped semiconductor substrate is formed. The semiconductor substrate includes a counterdoped drain region in the surface thereof and a channel alongside the sidewall. The drain region has a top level and a bottom level. A counterdoped source region is formed in the substrate juxtaposed with the sidewall below the channel. A gate oxide layer is formed on the sidewalls of the trench juxtaposed with a gate conductor. Perform the step of recessing the gate conductor below the bottom level of the drain region followed by performing angled ion implantation at an angle θ+δ with respect to vertical of a counterdopant into the channel below the source region and performing angled ion implantation at an angle θ with respect to vertical of a dopant into the channel below the source region

摘要翻译： 提供了形成深沟槽垂直晶体管的方法。 在掺杂半导体衬底中形成具有侧壁的深沟槽。 半导体衬底在其表面中包括反向漏极区域和沿着侧壁的通道。 漏极区域具有顶层和底层。 反向掺杂的源极区域形成在与通道下方的侧壁并置的衬底中。 栅极氧化层形成在与栅极导体并置的沟槽的侧壁上。 执行将栅极导体凹入低于漏极区域的底部电平的步骤，然后相对于反向掺杂物的垂直角进行成角度的离子注入进入源极区域下方的沟道，并以一定角度进行成角度的离子注入 相对于掺杂剂的垂直方向在源极区域下方的沟道中

公开(公告)号：US08232603B2

公开(公告)日：2012-07-31

申请号：US12702380

申请日：2010-02-09

申请人： Anthony I. Chou ,  Gregory G. Freeman ,  Kevin McStay ,  Shreesh Narasimha

发明人： Anthony I. Chou ,  Gregory G. Freeman ,  Kevin McStay ,  Shreesh Narasimha

IPC分类号： H01L21/70

CPC分类号： H01L21/28518 ,  H01L21/76829 ,  H01L29/66356 ,  H01L29/7391

摘要： A gated diode structure and a method for fabricating the gated diode structure use a relaxed liner that is derived from a stressed liner that is typically used within the context of a field effect transistor formed simultaneously with the gated diode structure. The relaxed liner is formed incident to treatment, such as ion implantation treatment, of the stressed liner. The relaxed liner provides improved gated diode ideality in comparison with the stressed liner, absent any gated diode damage that may occur incident to stripping the stressed liner from the gated diode structure while using a reactive ion etch method.

摘要翻译： 门控二极管结构和用于制造门控二极管结构的方法使用从应力衬里导出的松弛衬垫，其通常用于与栅极二极管结构同时形成的场效应晶体管的上下文中。 复杂的衬垫与应力衬里的处理（例如离子注入处理）形成。 与使用反应离子蚀刻方法相比，轻松的衬垫与应力衬里相比提供了改进的门控二极管理想，没有任何门控二极管损坏，其可能发生在从选通二极管结构剥离应力衬垫的同时发生。