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公开(公告)号：US20220037057A1
公开(公告)日：2022-02-03
申请号：US16983489
申请日：2020-08-03
申请人： DELL PRODUCTS, LP
发明人： Sandor Farkas , Bhyrav M. Mutnury
摘要： A dual axial cable includes first and second signal conductors and a shield. The first and second signal conductors transmit a differential signal. The shield includes a foil wrap spirally wrapped around the first and second conductors to form a plurality of foil wrap sections. Each of the foil wrap sections overlaps an adjacent foil wrap section. The periodicity of a pitch of each of the overlaps varies along a length of the dual axial cable.
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公开(公告)号：US20210271311A1
公开(公告)日：2021-09-02
申请号：US16804784
申请日：2020-02-28
申请人： DELL PRODUCTS, LP
IPC分类号： G06F1/3234 , G06F13/16
摘要： An information handling system includes a control processing unit (CPU) including a dual in-line memory module (DIMM) controller and hosting a basic input output system (BIOS). A first and a second set of DIMMs are connected to the CPU through the DIMM controller and by a first communication channel and a second communication channel, respectively. Each DIMM in the first and second set of DIMMs may be configured by the BIOS to include a unique data bus IO voltage (Vddq) setting for bidirectional communications with the CPU.
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公开(公告)号：US11068778B2
公开(公告)日：2021-07-20
申请号：US15152073
申请日：2016-05-11
申请人： DELL PRODUCTS, LP
IPC分类号： G06N3/08 , G06F30/394
摘要： A method includes training an artificial neural network with training data that comprises a sets of design parameter values for design parameters for circuit traces in a high speed communication link, determining an output formula that relates a sets of design parameters to a corresponding output parameter for the circuit traces in response to training the artificial neural network, running the output formula using a second set of design parameter values to obtain a corresponding set of output parameters for the circuit traces, determining that the corresponding set of output parameters differ from a set of modeled output parameters by less than a predefined percentage, and fabricating a circuit trace in a printed circuit board based upon the output formula in response to determining that the corresponding set of output parameters differ from the set of modeled output parameters by less than the predefined percentage.
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公开(公告)号：US20200337149A1
公开(公告)日：2020-10-22
申请号：US16385569
申请日：2019-04-16
申请人： DELL PRODUCTS, LP
发明人： Sandor Farkas , Bhyrav M. Mutnury
摘要： A printed circuit board includes first and second signal pads, and first, second, and third ground pads. The first and second signal pads and the first and second ground pads are arranged in a line with the first and second signal pads between the first and second ground pads. The third ground pad is arranged between the first and second signal pads but is not in line with the first and second signal pads.
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5.发明申请公开(公告)号：US20190289710A1
公开(公告)日：2019-09-19
申请号：US15923494
申请日：2018-03-16
申请人： DELL PRODUCTS, LP
摘要： A printed circuit board includes a differential signal via pairs to route differential signal between layers of the printed circuit board. A first differential signal via pair is oriented in a first orientation and a second differential signal via pair is oriented perpendicular to the first orientation. The second differential signal via pair is located such that a midpoint of a first line segment drawn between centers of first and second vias of the second differential signal pair intersects a first ray drawn from a center of a first via of the first differential signal via pair through a center of a second via of the first differential signal via pair. Further, the second differential signal via pair is located such that the midpoint of the first line segment is at a characteristic via-to-via pitch distance for the printed circuit board from the center of the second via of the first differential signal via pair.
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6.发明授权公开(公告)号：US10394725B2
公开(公告)日：2019-08-27
申请号：US15362431
申请日：2016-11-28
申请人： DELL PRODUCTS, LP
摘要： A process may involve assembling a device at a device assembler. The process may include receiving a set of components, where each component of the set of components may be associated with a respective memory storing a set of characteristics of the component. The process may include assembling the set of components into the device at the device assembler. The process may also include accessing each respective memory of the components to read the sets of characteristics stored in the respective memories, and determining from the sets of characteristics of the components the characteristics of the device.
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7.发明申请公开(公告)号：US20190227885A1
公开(公告)日：2019-07-25
申请号：US15876866
申请日：2018-01-22
申请人： DELL PRODUCTS, LP
摘要： A dynamic random access memory (DRAM) device includes an on-die termination (ODT) controller including an input to receive an ODT signal from a memory controller, and ODT circuitry to terminate an interface circuit, the interface circuit to provide a data signal between the memory controller and the DRAM device. The ODT controller is configured in a first impedance switching mode to terminate the interface circuit at a first impedance level in response to a first state of the ODT signal, to terminate the interface circuit at a second impedance level in response to a second state of the ODT signal, and to terminate the interface circuit at a third impedance level in response to a change in the ODT signal from the first state to the second state, the third impedance level being between the first impedance level and the second impedance level.
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公开(公告)号：US10298420B1
公开(公告)日：2019-05-21
申请号：US15926525
申请日：2018-03-20
申请人： DELL PRODUCTS, LP
发明人： Arun R. Chada , Han Deng , Bhyrav M. Mutnury
摘要： A high-speed serial data interface includes a transmitter and a receiver. The transmitter includes a feed-forward equalization (FFE) module. The FFE module has a main tap and at least one secondary tap. In a first mode, a sum of absolute values of a main tap compensation value and a secondary tap compensation value of each one of the at least one secondary tap is equal to one. In a second mode, the main tap compensation value has a unity gain equal to one, and each secondary tap compensation value is greater than or equal to the secondary tap compensation value in the first mode divided by the main tap compensation value in the first mode.
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公开(公告)号：US10292266B2
公开(公告)日：2019-05-14
申请号：US15963625
申请日：2018-04-26
申请人： DELL PRODUCTS, LP
摘要： A circuit board includes first and second lines of surface mount pads, and a trace. The surface mount pads within the first line extend from a first edge of the circuit board toward a second edge of the circuit board. The surface mount pads within the second line extend from the first edge of the circuit board toward the second edge of the circuit board, and the surface mount pads within the second line are further from a third edge of the circuit board as compared to the surface mount pads within the first line. The trace is located on a top surface of the circuit board, and extends from the third edge to a fourth edge of the circuit board. The spacing between first adjacent surface mount pads within the first line enables the trace to be routed between the first adjacent surface mount pads with less crosstalk between signals on the trace and signals on the surface mount pads within the first line.
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10.发明申请公开(公告)号：US20180321845A1
公开(公告)日：2018-11-08
申请号：US15588234
申请日：2017-05-05
申请人： DELL PRODUCTS, LP
摘要： An information handling system may include a processing unit and a memory device. The processing unit includes a memory controller and is configured to host a BIOS. The memory device is communicatively connected to the memory controller by a communication channel and stores memory device information. The BIOS obtains the memory device information and sets an equalization of the communication channel based on the memory device information. The BIOS may further set the equalization of the communication channel based on parameters of the communication channel.
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