公开(公告)号：US20080020230A1

公开(公告)日：2008-01-24

申请号：US11865215

申请日：2007-10-01

申请人： Daniel Edelstein ,  Edward Cooney ,  John Fitzsimmons ,  Jeffrey Gambino ,  Anthony Stamper

发明人： Daniel Edelstein ,  Edward Cooney ,  John Fitzsimmons ,  Jeffrey Gambino ,  Anthony Stamper

IPC分类号： B32B15/00 ,  B05D1/36

CPC分类号： H01L23/53238 ,  H01L23/5226 ,  H01L2924/0002 ,  Y10T428/12493 ,  H01L2924/00

摘要： Improved mechanical and adhesive strength and resistance to breakage of copper integrated circuit interconnections is obtained by forming a copper alloy in a copper via/wiring connection in an integrated circuit while minimizing adverse electrical effects of the alloy by confining the alloy to an interfacial region of said via/wiring connection and not elsewhere by a barrier which reduces or substantially eliminates the thickness of alloy in the conduction path. The alloy location and composition are further stabilized by reaction of all available alloying material with copper, copper alloys or other metals and their alloys.

摘要翻译： 通过在集成电路中的铜通孔/布线连接中形成铜合金，同时通过将合金限制在所述合金的界面区域来最小化合金的不利电效应来获得铜集成电路互连的改进的机械和粘合强度和断裂性 通孔/布线连接，而不在其他地方，通过减小或基本消除导电路径中合金的厚度。 通过所有可用的合金材料与铜，铜合金或其他金属及其合金的反应，合金位置和组成进一步稳定。

公开(公告)号：US20060027930A1

公开(公告)日：2006-02-09

申请号：US10710828

申请日：2004-08-05

申请人： Daniel Edelstein ,  Edward Cooney, III ,  John Fitzsimmons ,  Jeffrey Gambino ,  Anthony Stamper

发明人： Daniel Edelstein ,  Edward Cooney, III ,  John Fitzsimmons ,  Jeffrey Gambino ,  Anthony Stamper

IPC分类号： H01L23/48

CPC分类号： H01L23/53238 ,  H01L23/5226 ,  H01L2924/0002 ,  Y10T428/12493 ,  H01L2924/00

摘要： Improved mechanical and adhesive strength and resistance to breakage of copper integrated circuit interconnections is obtained by forming a copper alloy in a copper via/wiring connection in an integrated circuit while minimizing adverse electrical effects of the alloy by confining the alloy to an interfacial region of said via/wiring connection and not elsewhere by a barrier which reduces or substantially eliminates the thickness of alloy in the conduction path. The alloy location and composition are further stabilized by reaction of all available alloying material with copper, copper alloys or other metals and their alloys.

摘要翻译： 通过在集成电路中的铜通孔/布线连接中形成铜合金，同时通过将合金限制在所述合金的界面区域来最小化合金的不利电效应来获得铜集成电路互连的改进的机械和粘合强度和断裂性 通孔/布线连接，而不在其他地方，通过减小或基本消除导电路径中合金的厚度。 通过所有可用的合金材料与铜，铜合金或其他金属及其合金的反应，合金位置和组成进一步稳定。

公开(公告)号：US20050167838A1

公开(公告)日：2005-08-04

申请号：US10707996

申请日：2004-01-30

申请人： Daniel Edelstein ,  Matthew Colburn ,  Edward Cooney ,  Timothy Dalton ,  John Fitzsimmons ,  Jeffrey Gambino ,  Elbert Huang ,  Michael Lane ,  Vincent McGahay ,  Lee Nicholson ,  Satyanarayana Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas Shaw ,  Andrew Simon ,  Anthony Stamper

发明人： Daniel Edelstein ,  Matthew Colburn ,  Edward Cooney ,  Timothy Dalton ,  John Fitzsimmons ,  Jeffrey Gambino ,  Elbert Huang ,  Michael Lane ,  Vincent McGahay ,  Lee Nicholson ,  Satyanarayana Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas Shaw ,  Andrew Simon ,  Anthony Stamper

IPC分类号： H01L21/033 ,  H01L21/302 ,  H01L21/311 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L23/532 ,  H01L29/40

CPC分类号： B82Y30/00 ,  H01L21/0332 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

摘要： A method for manufacturing a structure includes providing a structure having an insulator layer with at least one interconnect and forming a sub lithographic template mask on the insulator layer. A selective etching step is used for etching the insulator layer through the sub lithographic template mask to form sub lithographic features near the at least one interconnect. A supra lithographic blocking mask may also be utilized. In another aspect, the method includes forming pinch off sections of sub lithographic size formed in a capping layer on the insulator layer. A semiconductor structure includes an insulator layer having at least one interconnect feature and at least one column formed in the insulator layer. A plurality of sub lithographic features formed on a top portion of the insulator layer and communicating with the at least one column is also provided. The plurality of sub lithographic features have a cross section or diameter less than any of the at least one column. A gap may be prohibited from forming on or near scribe lanes and vias

摘要翻译： 一种制造结构的方法包括提供具有至少一个互连的绝缘层的结构，并在绝缘体层上形成次光刻模板掩模。 选择性蚀刻步骤用于通过子光刻模板掩模蚀刻绝缘体层，以在至少一个互连附近形成亚光刻特征。 还可以使用超光刻阻挡掩模。 另一方面，该方法包括形成在绝缘体层上的覆盖层中形成的亚光刻尺寸的夹断部分。 半导体结构包括具有至少一个互连特征的绝缘体层和形成在绝缘体层中的至少一个列。 还提供了形成在绝缘体层的顶部并与至少一个柱连通的多个次级光刻特征。 所述多个亚光刻特征具有小于或小于所述至少一列中的任何一个的横截面或直径。 可能禁止在划线车道和通道上或附近形成间隙

公开(公告)号：US20060027929A1

公开(公告)日：2006-02-09

申请号：US11247818

申请日：2005-10-11

申请人： Edward Cooney ,  John Fitzsimmons ,  Jeffrey Gambino ,  Stephen Luce ,  Thomas McDevitt ,  Lee Nicholson ,  Anthony Stamper

发明人： Edward Cooney ,  John Fitzsimmons ,  Jeffrey Gambino ,  Stephen Luce ,  Thomas McDevitt ,  Lee Nicholson ,  Anthony Stamper

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L23/58

CPC分类号： H01L21/76831 ,  H01L21/02107 ,  H01L21/02203 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/02362 ,  H01L21/3105 ,  H01L21/31116 ,  H01L21/31695 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76826 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76868

摘要： Methods and structures having pore-closing layers for closing exposed pores in a patterned porous low-k dielectric layer, and optionally a reactive liner on the low-k dielectric. A first reactant is absorbed or retained in exposed pores in the patterned dielectric layer and then a second reactant is introduced into openings such that it enters the exposed-pores, while first reactant molecules are simultaneously being outgassed. The second reactant reacts in-situ with the outgassed first reactant molecules at a mouth region of the exposed pores to form the pore-closing layer across the mouth region of exposed pores, while retaining a portion of each pore's porosity to maintain characteristics and properties of the porous low-k dielectric layer. Optionally, the first reactant may be adsorbed onto the low-k dielectric such that upon introduction of the second reactant Into the patterned dielectric openings, a reactive liner is also formed on the low-k dielectric.

公开(公告)号：US20050266698A1

公开(公告)日：2005-12-01

申请号：US10709747

申请日：2004-05-26

申请人： Edward Cooney ,  John Fitzsimmons ,  Jeffrey Gambino ,  Stephen Luce ,  Thomas McDevitt ,  Lee Nicholson ,  Anthony Stamper

发明人： Edward Cooney ,  John Fitzsimmons ,  Jeffrey Gambino ,  Stephen Luce ,  Thomas McDevitt ,  Lee Nicholson ,  Anthony Stamper

IPC分类号： H01L21/31 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/316 ,  H01L21/469 ,  H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/76831 ,  H01L21/02107 ,  H01L21/02203 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/02362 ,  H01L21/3105 ,  H01L21/31116 ,  H01L21/31695 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76826 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76868

摘要： Methods and structures having pore-closing layers for closing exposed pores in a patterned porous low-k dielectric layer, and optionally a reactive liner on the low-k dielectric. A first reactant is absorbed or retained in exposed pores in the patterned dielectric layer and then a second reactant is introduced into openings such that it enters the exposed pores, while first reactant molecules are simultaneously being outgassed. The second reactant reacts in-situ with the outgassed first reactant molecules at a mouth region of the exposed pores to form the pore-closing layer across the mouth region of exposed pores, while retaining a portion of each pore's porosity to maintain characteristics and properties of the porous low-k dielectric layer. Optionally, the first reactant may be adsorbed onto the low-k dielectric such that upon introduction of the second reactant into the patterned dielectric openings, a reactive liner is also formed on the low-k dielectric.

摘要翻译： 具有闭孔层的方法和结构，用于封闭图案化的多孔低k电介质层中的暴露孔，以及可选地在低k电介质上的反应性衬垫。 第一反应物被吸收或保留在图案化介电层中的暴露孔中，然后将第二反应物引入开口中，使得其进入暴露的孔，同时第一反应物分子同时脱气。 第二反应物与暴露孔的口部区域处的脱气的第一反应物分子原位反应，以形成穿过暴露孔的口部区域的孔闭合层，同时保留每个孔隙的一部分以保持其孔的特性和性质 多孔低k电介质层。 任选地，第一反应物可以被吸附到低k电介质上，使得当将第二反应物引入图案化的电介质开口中时，还在低k电介质上形成反应性衬垫。

公开(公告)号：US20050098605A1

公开(公告)日：2005-05-12

申请号：US10702416

申请日：2003-11-06

申请人： Daniel Edelstein ,  John Fitzsimmons ,  Jeffrey Gambino ,  Anthony Stamper

发明人： Daniel Edelstein ,  John Fitzsimmons ,  Jeffrey Gambino ,  Anthony Stamper

IPC分类号： B23K20/00 ,  H01L23/485 ,  B23K37/00

CPC分类号： H01L24/85 ,  B23K20/007 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48463 ,  H01L2224/48609 ,  H01L2224/48611 ,  H01L2224/48644 ,  H01L2224/48709 ,  H01L2224/48711 ,  H01L2224/48744 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85359 ,  H01L2224/85801 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/01049 ,  H01L2924/00 ,  H01L2924/00015

摘要： A structure and method for low-pressure wirebonding, reducing the propensity of dielectric material to mechanical failure due to wirebond stress. A low temperature alloy on the surface of a bond pad allows alloy bond formation to occur between the wire and the bond pad at reduced bond pressures and reduced thermal and ultrasonic energies. Preferred alloys include Au—Sn and Au—In. The Au—Sn alloy may be formed over the Cu bond pad, incorporated in an aluminum bond pad stack, or deposited on a bond pad having Ni—Au capping of Cu or Al bond pads.

摘要翻译： 一种用于低压引线键合的结构和方法，降低了由于引线键应力导致的介电材料对机械故障的倾向。 接合焊盘表面上的低温合金允许在降低的接合压力和降低的热和超声能量的情况下在导线和接合焊盘之间形成合金结合。 优选的合金包括Au-Sn和Au-In。 Au-Sn合金可以形成在结合在铝焊盘叠层中的Cu焊盘上，或者沉积在具有Cu或Al键合焊盘的Ni-Au封盖的焊盘上。

公开(公告)号：US07704876B2

公开(公告)日：2010-04-27

申请号：US11847657

申请日：2007-08-30

申请人： Jeffrey Gambino ,  Edward Cooney, III ,  Anthony Stamper ,  William Thomas Motsiff ,  Michael Lane ,  Andrew Simon

发明人： Jeffrey Gambino ,  Edward Cooney, III ,  Anthony Stamper ,  William Thomas Motsiff ,  Michael Lane ,  Andrew Simon

IPC分类号： H01L21/4763

CPC分类号： H01L21/76811 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76813 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76865 ,  H01L21/76877 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods are disclosed for forming dual damascene back-end-of-line (BEOL) interconnect structures using materials for the vias or studs which are different from those used for the line conductors, or using materials for the via liner which are different from those used for the trench liner, or having a via liner thickness different from that of the trench liner. Preferably, a thick refractory metal is used in the vias for improved mechanical strength while using only a thin refractory metal in the trenches to provide low resistance.

摘要翻译： 公开了用于形成双镶嵌后端（BEOL）互连结构的方法，其使用与用于线路导体的那些不同的通孔或螺柱的材料，或者使用不同于所使用的通孔衬垫的材料 用于沟槽衬垫，或者具有不同于沟槽衬套的通孔衬垫厚度。 优选地，在通孔中使用厚的难熔金属以改善机械强度，同时仅在沟槽中使用薄的难熔金属来提供低电阻。

公开(公告)号：US07300867B2

公开(公告)日：2007-11-27

申请号：US11174985

申请日：2005-07-05

申请人： Jeffrey Gambino ,  Edward Cooney, III ,  Anthony Stamper ,  William Thomas Motsiff ,  Michael Lane ,  Andrew Simon

发明人： Jeffrey Gambino ,  Edward Cooney, III ,  Anthony Stamper ,  William Thomas Motsiff ,  Michael Lane ,  Andrew Simon

IPC分类号： H01L21/4763

CPC分类号： H01L21/76811 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76813 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76865 ,  H01L21/76877 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods are disclosed for forming dual damascene back-end-of-line (BEOL) interconnect structures using materials for the vias or studs which are different from those used for the line conductors, or using materials for the via liner which are different from those used for the trench liner, or having a via liner thickness different from that of the trench liner. Preferably, a thick refractory metal is used in the vias for improved mechanical strength while using only a thin refractory metal in the trenches to provide low resistance.

摘要翻译： 公开了用于形成双镶嵌后端（BEOL）互连结构的方法，其使用与用于线路导体的那些不同的通孔或螺柱的材料，或者使用不同于所使用的通孔衬垫的材料 用于沟槽衬垫，或者具有不同于沟槽衬套的通孔衬垫厚度。 优选地，在通孔中使用厚的难熔金属以改善机械强度，同时仅在沟槽中使用薄的难熔金属来提供低电阻。

公开(公告)号：US06958540B2

公开(公告)日：2005-10-25

申请号：US10604026

申请日：2003-06-23

申请人： Jeffrey Gambino ,  Edward Cooney, III ,  Anthony Stamper ,  William Thomas Motsiff ,  Michael Lane ,  Andrew Simon

发明人： Jeffrey Gambino ,  Edward Cooney, III ,  Anthony Stamper ,  William Thomas Motsiff ,  Michael Lane ,  Andrew Simon

IPC分类号： H01L21/768 ,  H01L23/42 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76811 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76813 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76865 ,  H01L21/76877 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Interconnect structures are disclosed for forming dual damascene back-end-of-line (BEOL) structure using materials for the vias or studs which are different from those used for the line conductors, or using materials for the via liner which are different from those used for the trench liner, or having a via liner thickness different from that of the trench liner. Preferably, a thick refractory metal is used in the vias for improved mechanical strength while using only a thin refractory metal in the trenches to provide low resistance.

摘要翻译： 公开了用于形成双镶嵌后端（BEOL）结构的互连结构，其使用与用于线路导体的那些不同的通孔或螺柱的材料，或者使用不同于所使用的通孔衬垫的材料 用于沟槽衬垫，或者具有不同于沟槽衬套的通孔衬垫厚度。 优选地，在通孔中使用厚的难熔金属以改善机械强度，同时仅在沟槽中使用薄的难熔金属来提供低电阻。

公开(公告)号：US20070181974A1

公开(公告)日：2007-08-09

申请号：US11307404

申请日：2006-02-06

申请人： Douglas Coolbaugh ,  Timothy Dalton ,  Daniel Edelstein ,  Ebenezer Eshun ,  Jeffrey Gambino ,  Kevin Petrarca ,  Anthony Stamper ,  Richard Volant

发明人： Douglas Coolbaugh ,  Timothy Dalton ,  Daniel Edelstein ,  Ebenezer Eshun ,  Jeffrey Gambino ,  Kevin Petrarca ,  Anthony Stamper ,  Richard Volant

IPC分类号： H01L29/00 ,  H01L21/20

CPC分类号： H01L28/20 ,  H01L23/5228 ,  H01L23/53238 ,  H01L23/53295 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

摘要： Resistors that avoid the problems of miniaturization of semiconductor devices and a related method are disclosed. In one embodiment, a resistor includes a planar resistor material that extends vertically within at least one metal layer of a semiconductor device. In another embodiment, a resistor includes a resistor material layer extending between a first bond pad and a second bond pad of a semiconductor device. The two embodiments can be used alone or together. A related method for generating the resistors is also disclosed.

摘要翻译： 公开了避免半导体器件小型化的问题的电阻器及相关方法。 在一个实施例中，电阻器包括在半导体器件的至少一个金属层内垂直延伸的平面电阻器材料。 在另一个实施例中，电阻器包括在半导体器件的第一接合焊盘和第二接合焊盘之间延伸的电阻材料层。 这两个实施方案可以单独使用或一起使用。 还公开了用于产生电阻器的相关方法。