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    Method and system for ensuring the assertion order of signals in a chip independent of physical layout
    7.
    发明授权
    Method and system for ensuring the assertion order of signals in a chip independent of physical layout 有权

    公开(公告)号：US07102397B2

    公开(公告)日：2006-09-05

    申请号：US10961015

    申请日：2004-10-08

    申请人： James D. Sweet

    发明人： James D. Sweet

    IPC分类号： H03L7/00

    CPC分类号： H03K19/1731 ,  G01R31/31701

    摘要： Certain embodiments for ensuring the assertion order of signals in a chip independent of physical layout may comprise receiving a first signal by a first logic block of a plurality of logic blocks integrated within a chip, where the first signal may initiate a reset of a first function within the first logic block. A second signal may be communicated from within the first logic block to a second function within a second logic block of the plurality of logic blocks, and the second signal may be adapted to initiate the second function. The first signal may be the same as a second signal. The reset of the first function may initialize the first function to a known state before the second function may generate an output that may be received by the first function. The first function may place the chip in a test mode when indicated by the generated output of the second function.

    Testing of integrated circuits from design documentation
    8.
    发明授权
    Testing of integrated circuits from design documentation 失效
    从设计文件测试集成电路

    公开(公告)号：US06978216B2

    公开(公告)日：2005-12-20

    申请号：US10703729

    申请日：2003-11-07

    申请人： James D. Sweet

    发明人： James D. Sweet

    IPC分类号： G01R31/3183 ,  G06F17/50 ,  G06F19/00

    CPC分类号： G01R31/318357 ,  G01R31/318342 ,  G06F17/5022

    摘要： One or more methods and systems of validating the operation of one or more register designs are presented. In one embodiment, the system utilizes a processor, an integrated circuit design simulator software, a storage media, a storage device, user interface, and a display. In one embodiment, the method includes executing a set of instructions operating on a register design parameter file to produce an output that is easily incorporated into the integrated circuit design simulator software. The output specifies one or more tests to be performed using the integrated circuit design simulator software. The one or more tests are subsequently performed to validate the register design. The method automates the incorporation of register design parameters into the integrated circuit design simulator software by way of executing a set of instructions that operates on the register design parameter file.

    摘要翻译： 提出一种或多种验证一个或多个寄存器设计的操作的方法和系统。 在一个实施例中，系统利用处理器，集成电路设计模拟器软件，存储介质，存储设备，用户界面和显示器。 在一个实施例中，该方法包括执行在寄存器设计参数文件上操作的一组指令以产生易于并入到集成电路设计仿真器软件中的输出。 输出指定使用集成电路设计模拟器软件执行的一个或多个测试。 随后执行一个或多个测试以验证寄存器设计。 该方法通过执行对寄存器设计参数文件进行操作的一组指令来自动将寄存器设计参数并入到集成电路设计仿真器软件中。