公开(公告)号：US5555384A

公开(公告)日：1996-09-10

申请号：US324861

申请日：1994-10-18

申请人： David B. Roberts ,  George S. Taylor ,  David M. Parry

发明人： David B. Roberts ,  George S. Taylor ,  David M. Parry

IPC分类号： G06F9/38

CPC分类号： G06F9/3871 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/3828 ,  G06F9/3836 ,  G06F9/3857 ,  G06F9/3867 ,  G06F9/3873 ,  G06F9/3877

摘要： Methods and apparatus for optimizing the operation of an instruction pipeline in a computer are disclosed. The methods and apparatus function at both the effective beginning and end of the pipeline. At the pipeline's beginning, a Pipeline Controller monitors the availability of data for various floating point operations. Data is read at either a fast or slow rate, depending on its availability, and instructions are allowed to proceed through the pipeline based on this data availability. At the effective end of the pipeline, the Controller monitors all instructions in the pipeline, notes all potential resource conflicts, and resolves these potential conflicts by either the insertion of an appropriate number of HOLD states or the conclusion that no actual resource competition exists.

摘要翻译： 公开了一种用于优化计算机中的指令流水线操作的方法和装置。 该方法和装置在管道的有效开始和结束时起作用。 管道开始时，管道控制器监视各种浮点运算的数据可用性。 数据以快速或慢速读取，具体取决于其可用性，并且允许指令基于此数据可用性进行管道。 在管道的有效端，控制器监视所有正在运行的指令，注意所有潜在的资源冲突，并通过插入适当数量的HOLD状态或不存在实际资源竞争的结论来解决这些潜在的冲突。

公开(公告)号：US5822381A

公开(公告)日：1998-10-13

申请号：US435455

申请日：1995-05-05

申请人： David M. Parry ,  Charles E. Narad ,  Daniel E. Lenoski

发明人： David M. Parry ,  Charles E. Narad ,  Daniel E. Lenoski

IPC分类号： G06F1/10 ,  H04J3/06 ,  H04L7/02

CPC分类号： G06F1/10 ,  H04J3/0641

摘要： A clock system for a distributed multiprocessor system includes a plurality of local clock circuits and a distribution network. The distribution network includes a plurality of interconnected routers. Each local clock circuit is associated with a processing node of the multiprocessor system. Each local clock circuit generates a global clock source signal, provides the global clock source signal to the distribution network, receives a global clock signal back from the distribution network, and generates a global time value based on a local clock signal and the global clock signal. The router is part of the distribution network of the multiprocessor system. The router receives the global clock source signals from each of the local clock circuits, selects one of the global clock source signals as the global clock signal and provides the global clock signal to the distribution network for distribution to each of the local clock circuits.

摘要翻译： 用于分布式多处理器系统的时钟系统包括多个本地时钟电路和分配网络。 分配网络包括多个互连的路由器。 每个本地时钟电路与多处理器系统的处理节点相关联。 每个本地时钟电路产生全局时钟源信号，将全局时钟源信号提供给分配网络，从分配网络接收全局时钟信号，并根据本地时钟信号和全局时钟信号产生全局时间值 。 路由器是多处理器系统分发网络的一部分。 路由器接收来自每个本地时钟电路的全局时钟源信号，选择全局时钟源信号之一作为全局时钟信号，并将全局时钟信号提供给分配网络以分配给每个本地时钟电路。

公开(公告)号：US06529570B1

公开(公告)日：2003-03-04

申请号：US09409768

申请日：1999-09-30

申请人： Steven C. Miller ,  Michael B. Galles ,  David M. Parry ,  Jon C. Gibbons

发明人： Steven C. Miller ,  Michael B. Galles ,  David M. Parry ,  Jon C. Gibbons

IPC分类号： H04L700

CPC分类号： H04L7/02

摘要： A data synchronizer (60) receives a data ready signal (40) at a selector (82). The selector (82) selects either the data ready signal (40) or a delayed version of the data ready signal (40) in response to a speed select signal (88) determined according to a clock speed of a receive core clock (52). The selector (82) provides a select signal (92) to a first latch unit (94) and a second latch unit (96). The first latch unit (94) generates a latched select signal (A) that is provided as a receive data valid signal (48) by a signal generator (108) in response to a slow clock rate for the receive core clock (52). The second latch unit (96) generates a delayed select signal (B) that is used by the signal generator (108) to remove an extra width inserted into the latched select signal (A) prior to providing the receive data valid signal (48) in response to a fast clock rate for the receive core clock (52).

摘要翻译： 数据同步器（60）在选择器（82）处接收数据就绪信号（40）。 响应于根据接收核心时钟（52）的时钟速度确定的速度选择信号（88），选择器（82）选择数据就绪信号（40）或数据就绪信号（40）的延迟版本， 。 选择器（82）向第一锁存单元（94）和第二锁存单元（96）提供选择信号（92）。 第一锁存单元（94）响应于接收核心时钟（52）的慢时钟速率产生由信号发生器（108）作为接收数据有效信号（48）提供的锁存选择信号（A）。 第二锁存单元（96）在提供接收数据有效信号（48）之前产生延迟选择信号（B），该延迟选择信号由信号发生器（108）用来去除插入锁存选择信号（A）中的额外宽度， 响应于所述接收核心时钟（52）的快速时钟速率。