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公开(公告)号：US5754131A
公开(公告)日：1998-05-19
申请号：US673543
申请日：1996-07-01
摘要： A delta sigma modulator that has a low power dissipation without sacrificing modulator resolution includes, in one embodiment, a current mode digital to analog converter (DAC) in shunt with a conventional op amp in the first stage of the delta sigma modulator. By adding the current mode DAC in shunt with the first (or only) stage op amp of the delta sigma modulator, the slewing current needed during transients is provided by the combination of the op amp and DAC output signals. Since the DAC provides the slewing current required for the output signal change, the op amp need not apply the slewing current and therefore need only operate at low quiescent power.
摘要翻译： 在一个实施例中，具有低功耗而不牺牲调制器分辨率的ΔΣ调制器包括与ΔΣ调制器的第一级中的常规运算放大器分流的电流模式数模转换器（DAC）。 通过将电流模式DAC与Δ-Σ调制器的第一（或仅））级运算放大器并联，瞬态期间所需的回转电流由运算放大器和DAC输出信号的组合提供。 由于DAC提供输出信号变化所需的回转电流，因此运算放大器不需要使用回转电流，因此只需要在低静态功率下工作。
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公开(公告)号：US5682161A
公开(公告)日：1997-10-28
申请号：US650281
申请日：1996-05-20
摘要： A delta-sigma modulator includes, in one embodiment, cascaded unit-delay integrators, the number of which is selected depending upon the order desired. The modulator further includes an n-bit (or multi-bit) A/D converter coupled to the output of the last cascaded integrator, and an n-bit (or multi-bit) D/A converter coupled to the output of the A/D converter. A truncator also is coupled to the output of the A/D converter. Truncation error correction is performed digitally by a truncation corrector. A one-bit D/A converter provides feedback from the output of the truncator to differential summing junctions interposed at the input of each unit-delay integrator. The multi-bit D/A converter output signal is fed back to differential summing junctions at the input of the third order and higher unit-delay integrators. The multi-bit D/A converter requires no digital correction of its linearity and only unit-delay integrators are used so that N-1 delay free integrators do not all have to settle within one clock period. The modulator therefore utilizes multiple quantizer bits to provide increased converter resolution and is stable at high orders.
摘要翻译： 在一个实施例中，Δ-Σ调制器包括级联单元延迟积分器，其数量根据期望的顺序被选择。 调制器还包括耦合到最后级联积分器的输出端的n位（或多位）A / D转换器和耦合到A的输出的n位（或多位）D / A转换器 / D转换器。 截断器也耦合到A / D转换器的输出端。 截断误差校正由截断校正器数字地执行。 一位D / A转换器提供从截断器的输出到插入在每个单位延迟积分器的输入端的差分求和结点的反馈。 多位D / A转换器输出信号反馈到三阶输入端和较高单位延迟积分器的差分求和结点。 多位D / A转换器不需要其线性度的数字校正，并且仅使用单位延迟积分器，使得N-1个延迟自由积分器并不都必须在一个时钟周期内稳定。 因此，调制器利用多个量化器位来提供增加的转换器分辨率，并且在高阶下是稳定的。
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3.发明授权High-order delta sigma analog-to-digital converter with unit-delay integrators 失效具有单位延迟积分器的高阶Δ西格玛模数转换器
公开(公告)号：US5682160A
公开(公告)日：1997-10-28
申请号：US650282
申请日：1996-05-20
摘要： A delta sigma modulator which enables each cascaded integrator to settle independently within a full clock period and uses binomial coefficients in the feedback paths to obtain the required sinusoidal shaping of quantizer error, achieves an increase in both the sampling rate and the order to improve resolution. Using a multi-bit quantizer also improves modulator resolution. In one embodiment, the modulator includes a plurality of cascaded unit-delay integrators and utilizes binomial coefficient scaling in the feedback loop. A multi-bit analog-to-digital converter is coupled to receive the output signal of the cascaded unit-delay integrators. The feedback loop includes a multi-bit digital-to-analog converter coupled to the output of the multi-bit analog-to-digital converter. The output of the digital-to-analog converter is coupled to the inputs of at least the first and second differential summing junctions.
摘要翻译： 一个ΔΣ调制器使得每个级联积分器能够在一个完整的时钟周期内独立地稳定，并且使用反馈路径中的二项式系数来获得所需的量化器误差的正弦整形，实现了采样率和阶数的提高以提高分辨率。 使用多位量化器也可以提高调制器分辨率。 在一个实施例中，调制器包括多个级联的单位延迟积分器，并在反馈回路中利用二项式系数缩放。 多位模数转换器被耦合以接收级联单元延迟积分器的输出信号。 反馈回路包括耦合到多位模数转换器的输出的多位数模转换器。 数模转换器的输出耦合到至少第一和第二差分求和结的输入端。
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4.发明授权
公开(公告)号：US5757300A
公开(公告)日：1998-05-26
申请号：US734906
申请日：1996-10-22
摘要： Delta sigma modulators for accepting input signals having amplitudes up to -1 dB of full-scale and a center frequency (F.sub.S) in the range �F.sub.S /90, 44F 90!, and which are not prone to internal overflow, require few circuit parameters, and yield a signal transfer function with the inherent property that the modulator magnitude response is close to unity gain in the frequency region of interest include, in one embodiment, a pair of cascaded integrators, a unit delay element coupled to the output of the second integrator, an analog-to-digital (A/D) converter, and a one-bit digital-to-analog (D/A) converter controlled by output signals from the A/D converter. A first differential summing junction coupled to the output of the D/A converter is responsive to delta sigma modulator input signals. A second differential summing junction, coupled to the output of the first differential summing junction, is also coupled to receive a feedback signal from the second integrator. A third differential summing junction, coupled to the output of the unit delay element, also receives feed-forward signals from the second integrator.
摘要翻译： 用于接受具有高达-1dB的满量程的输入信号和在[FS / 90,44F 90]范围内且不易于内部溢出的中心频率（FS）的ΔΣ调制器需要很少的电路参数 ，并且产生具有固有特性的信号传递函数，调制器幅度响应在感兴趣的频率区域中接近于单位增益，在一个实施例中包括一对级联积分器，单元延迟元件耦合到第二 积分器，模拟（A / D）转换器和由A / D转换器的输出信号控制的1位数模转换器（D / A）转换器。 耦合到D / A转换器的输出的第一差分求和结点响应ΔΣ调制器输入信号。 耦合到第一差分求和结的输出的第二差分求和结还被耦合以从第二积分器接收反馈信号。 耦合到单元延迟元件的输出的第三差分求和结还接收来自第二积分器的前馈信号。
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公开(公告)号：US09153221B2
公开(公告)日：2015-10-06
申请号：US14022573
申请日：2013-09-10
申请人： David Byrd Ribner
发明人： David Byrd Ribner
摘要： Provided are a percussion instrument tuning system and method. A position sensor determines at least one first position of a tuning mechanism of a timpano. A control unit generates a calibration result by measuring a first pitch of the timpano corresponding to the at least one first position of the tuning mechanism and estimates a second pitch of the timpano corresponding to at least one second position of the tuning mechanism from the calibration result.
摘要翻译： 提供了一种打击乐器调音系统和方法。 位置传感器确定音标的调谐机构的至少一个第一位置。 控制单元通过测量与调谐机构的至少一个第一位置相对应的音标的第一音调来产生校准结果，并从校准结果估计对应于调谐机构的至少一个第二位置的音标的第二音调 。
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公开(公告)号：US08742242B1
公开(公告)日：2014-06-03
申请号：US13886342
申请日：2013-05-03
申请人： David Byrd Ribner
发明人： David Byrd Ribner
IPC分类号： G10G7/02
CPC分类号： G10G7/02 , G10D13/023
摘要： A processor of a tuning apparatus receives a desired fundamental frequency or note and determines a frequency or note of at least one drumhead of a drum in response to the received desired fundamental frequency or note. An output at the processor outputs a value corresponding to the determined frequency or note of the drumhead.
摘要翻译： 调谐装置的处理器接收期望的基本频率或音符，并响应于接收到的所需基频或音符确定鼓的至少一个鼓头的频率或音符。 处理器处的输出输出对应于确定的鼓头频率或音符的值。
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公开(公告)号：US20140069258A1
公开(公告)日：2014-03-13
申请号：US14022573
申请日：2013-09-10
申请人： David Byrd Ribner
发明人： David Byrd Ribner
摘要： Provided are a percussion instrument tuning system and method. A position sensor determines at least one first position of a tuning mechanism of a timpano. A control unit generates a calibration result by measuring a first pitch of the timpano corresponding to the at least one first position of the tuning mechanism and estimates a second pitch of the timpano corresponding to at least one second position of the tuning mechanism from the calibration result.
摘要翻译： 提供了一种打击乐器调音系统和方法。 位置传感器确定音标的调谐机构的至少一个第一位置。 控制单元通过测量与调谐机构的至少一个第一位置相对应的音标的第一音调来产生校准结果，并从校准结果估计对应于调谐机构的至少一个第二位置的音标的第二音高 。
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公开(公告)号：US6028891A
公开(公告)日：2000-02-22
申请号：US670337
申请日：1996-06-25
摘要： A discrete multi-tone, asymmetrical transceiver and method wherein a modem at a central office transmits information to a modem at a remote terminal on a down-stream signal and the modem at the remote terminal transmits information to the modem at the central office on an up-stream signal. The up-stream signal comprising data carried by a lower portion of a predetermined band of frequencies and the down-stream signal comprising data carried by an upper portion of the predetermined band of frequencies. The system includes an interpolator, at the remote terminal, for adding interpolated data into a stream of data distributed by the remote terminal modem among the lower portion of the predetermined band of frequencies for transmission in the up-stream signal. An ADC is provided at the modem of the central office, for converting the down-stream signal into digital samples at a sampling rate greater than the frequency of the highest frequency in the down-stream signal. A decimator is fed samples from the ADC at the ADC sampling rate and produces output samples at a lower sampling rate. A demodulator is fed the samples produced by the decimator at the lower sampling rate and converts such samples into the lower portion of the predetermined band of frequencies. The interpolator increases the rate of samples produced on the up-stream signal and thereby increases the frequency of images in such up-stream signal for more effective removal by the band pass filter of the remote terminal. Images in the up-stream signal which may couple into the receiver at the central office are increased in frequency and then are effective filtering by the decimator.
摘要翻译： 一种离散的多音调，不对称收发器和方法，其中中心局的调制解调器向下行信号的远程终端向调制解调器发送信息，并且远程终端上的调制解调器向中心局的调制解调器发送信息 上行信号。 上行信号包括由预定频带的下部承载的数据，下行信号包括由预定频带的上部承载的数据。 该系统包括在远程终端处的内插器，用于将内插数据添加到由预定频带的下部分中的由远程终端调制解调器分配的数据流中，以在上行信号中传输。 在中心局的调制解调器处提供ADC，用于将下行流信号以大于下行信号中最高频率的频率的采样率转换成数字采样。 抽取器以ADC采样率从ADC馈送采样，并以较低的采样率产生输出采样。 解调器以较低采样率馈送由抽取器产生的样本，并将这些样本转换成预定频带的下部。 内插器增加在上行信号上产生的样本的速率，从而增加这种上行信号中的图像的频率，以便远程终端的带通滤波器更有效地去除。 可能在中心局耦合到接收机中的上行信号中的图像的频率增加，然后由抽取器进行有效的滤波。
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公开(公告)号：US20140165818A1
公开(公告)日：2014-06-19
申请号：US13886342
申请日：2013-05-03
申请人： David Byrd Ribner
发明人： David Byrd Ribner
IPC分类号： G10G7/02
CPC分类号： G10G7/02 , G10D13/023
摘要： Disclosed is a tuning apparatus comprising a processor that receives a desired fundamental frequency or note and determines a frequency of at least one drumhead of a drum in response to the received desired fundamental frequency or note and a display that presents a value corresponding to the determined frequency of the drumhead.
摘要翻译： 公开了一种调谐装置，包括处理器，其接收期望的基本频率或音符，并且响应于接收到的期望基频或音符和显示对应于所确定的频率的值来确定鼓的至少一个鼓头的频率 的鼓掌。
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公开(公告)号：US08642874B2
公开(公告)日：2014-02-04
申请号：US13004166
申请日：2011-01-11
申请人： David Byrd Ribner
发明人： David Byrd Ribner
摘要： A resonance tuner receives and digitizes an analog signal in response to a resonance of a structure thereby creating a plurality of time samples. A series of the time samples are buffered upon burst detection. A power spectrum is estimated by computing a Time-To-Frequency-Transform of the series of time samples and a magnitude of each of the resulting frequency samples is squared. At least one subset associated with at least one spectral peak is selected from the frequency samples. Each spectral peak has at least one sample with a sufficient magnitude and being spectrally adjacent to any other sample in another spectral peak by less than a threshold. A fundamental spectral peak is determined in a fundamental subset including a spectral peak with a sample at the lowest frequency greater than zero. The fundamental spectral peak has the sample with the largest magnitude within the fundamental subset.
摘要翻译： 谐振调谐器响应于结构的谐振而接收并数字化模拟信号，从而产生多个时间样本。 一系列时间样本在突发检测时被缓冲。 通过计算一系列时间样本的时间 - 频率变换来估计功率谱，并且所得到的每个频率样本的幅度平方。 从频率样本中选择与至少一个频谱峰值相关联的至少一个子集。 每个光谱峰值具有至少一个具有足够大小的样本，并且在另一个光谱峰值中的任何其他样本频谱相邻小于阈值。 在基本子集中确定基本谱峰，包括具有大于零的最低频率的样本的光谱峰。 基本谱峰具有基本子集内具有最大幅度的样本。
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