公开(公告)号：US20100284140A1

公开(公告)日：2010-11-11

申请号：US12839094

申请日：2010-07-19

申请人： David J. Corisis ,  Lee Choon Kuan ,  Chin Hui Chong

发明人： David J. Corisis ,  Lee Choon Kuan ,  Chin Hui Chong

IPC分类号： H05K1/11 ,  G06F1/16

CPC分类号： H05K1/115 ,  G01R31/026 ,  G06F1/16 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2223/6638 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/0221 ,  H05K1/0245 ,  H05K1/0251 ,  H05K1/0296 ,  H05K1/18 ,  H05K3/42 ,  H05K3/429 ,  H05K2201/09236 ,  H05K2201/09672 ,  H05K2201/09809 ,  Y10T29/49165 ,  H01L2924/00

摘要： Electronic devices include a substrate with first and second pairs of conductive traces extending in or on the substrate. A first conductive interconnecting member extends through a hole in the substrate and communicates electrically with a first trace of each of the first and second pairs, while a second conductive interconnecting member extends through the hole and communicates electrically with the second trace of each of the first and second pairs. The first and second interconnecting members are separated from one another by a distance substantially equal to a distance separating the conductive traces in each pair. Electronic device assemblies include a transmitting device configured to transmit a differential signal through a conductive structure to a receiving device. The conductive structure includes first and second pair of conductive traces with first and second interconnecting members providing electrical communication therebetween.

摘要翻译： 电子器件包括具有在衬底中或衬底上延伸的第一和第二对导电迹线的衬底。 第一导电互连构件延伸穿过衬底中的孔并且与第一和第二对中的每一个的第一迹线电连通，而第二导电互连构件延伸穿过孔并与第一导电互连构件中的每一个的第二迹线电连通 和第二对。 第一和第二互连构件彼此间隔开距离，该距离基本上等于分隔每对导电迹线的距离。 电子设备组件包括被配置为通过导电结构将差分信号传输到接收设备的发送设备。 导电结构包括第一和第二对导电迹线，其中第一和第二互连构件之间提供电连通。

公开(公告)号：US07767913B2

公开(公告)日：2010-08-03

申请号：US11359863

申请日：2006-02-22

申请人： David J. Corisis ,  Lee Choon Kuan ,  Chin Hui Chong

发明人： David J. Corisis ,  Lee Choon Kuan ,  Chin Hui Chong

IPC分类号： H01R12/04 ,  H05K1/11

CPC分类号： H05K1/115 ,  G01R31/026 ,  G06F1/16 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2223/6638 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/0221 ,  H05K1/0245 ,  H05K1/0251 ,  H05K1/0296 ,  H05K1/18 ,  H05K3/42 ,  H05K3/429 ,  H05K2201/09236 ,  H05K2201/09672 ,  H05K2201/09809 ,  Y10T29/49165 ,  H01L2924/00

摘要： Electronic devices include a substrate with first and second pairs of conductive traces extending in or on the substrate. A first conductive interconnecting member extends through a hole in the substrate and communicates electrically with a first trace of each of the first and second pairs, while a second conductive interconnecting member extends through the hole and communicates electrically with the second trace of each of the first and second pairs. The first and second interconnecting members are separated from one another by a distance substantially equal to a distance separating the conductive traces in each pair. Electronic device assemblies include a transmitting device configured to transmit a differential signal through a conductive structure to a receiving device. The conductive structure includes first and second pair of conductive traces with first and second interconnecting members providing electrical communication therebetween.

摘要翻译： 电子器件包括具有在衬底中或衬底上延伸的第一和第二对导电迹线的衬底。 第一导电互连构件延伸穿过衬底中的孔并且与第一和第二对中的每一个的第一迹线电连通，而第二导电互连构件延伸穿过孔并与第一导电互连构件中的每一个的第二迹线电连通 和第二对。 第一和第二互连构件彼此间隔开距离，该距离基本上等于分隔每对导电迹线的距离。 电子设备组件包括被配置为通过导电结构将差分信号传输到接收设备的发送设备。 导电结构包括第一和第二对导电迹线，其中第一和第二互连构件之间提供电连通。

公开(公告)号：US20080136001A1

公开(公告)日：2008-06-12

申请号：US12020899

申请日：2008-01-28

申请人： David J. Corisis ,  Lee Choon Kuan ,  Chong Chin Hui

发明人： David J. Corisis ,  Lee Choon Kuan ,  Chong Chin Hui

IPC分类号： H01L23/31

CPC分类号： H01L23/3107 ,  H01L21/568 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85001 ,  H01L2224/97 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2924/207

摘要： Disclosed is a carrierless chip package for integrated circuit devices, and various methods of make same. In one illustrative embodiment, the device includes an integrated circuit chip comprising an exposed backside surface defining a plane, a plurality of wire bonds that are conductively coupled to the integrated circuit chip, each of the plurality of wire bonds being conductively coupled to a conductive exposed portion, a portion of the conductive exposed portion being positioned in the plane defined by the backside surface, and an encapsulant material positioned adjacent the integrated circuit chip and the plurality of wire bonds.

摘要翻译： 公开了用于集成电路器件的无载体芯片封装，以及制造相同的各种方法。 在一个说明性实施例中，该器件包括集成电路芯片，该集成电路芯片包括限定平面的暴露的背面，与该集成电路芯片导电耦合的多个引线键合，多个引线键合中的每一个导电耦合到导电暴露 导电暴露部分的一部分位于由背侧表面限定的平面中，以及邻近集成电路芯片定位的密封材料和多个引线键合。

公开(公告)号：US08125092B2

公开(公告)日：2012-02-28

申请号：US12107622

申请日：2008-04-22

申请人： David J. Corisis ,  Lee Choon Kuan ,  Chong Chin Hui

发明人： David J. Corisis ,  Lee Choon Kuan ,  Chong Chin Hui

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/3128 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06575 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device package includes a carrier, one or more semiconductor devices on the carrier, and a redistribution element above the uppermost of the one or more semiconductor devices. The redistribution element includes an array of contact pads that communicate with each semiconductor device of the package. The package may also include an encapsulant through which the contact pads of the redistribution element are at least electrically exposed. Methods for assembling and packaging semiconductor devices, as well as methods for assembling multiple packages, including methods for replacing the functionality of one or more defective semiconductor devices of a package according to embodiments of the present invention, are also disclosed.

摘要翻译： 半导体器件封装包括载体，载体上的一个或多个半导体器件，以及位于该一个或多个半导体器件的最上面的再分配元件。 再分配元件包括与封装的每个半导体器件通信的接触焊盘阵列。 封装还可以包括密封剂，再分配元件的接触垫至少通过电子暴露于其中。 还公开了用于组装和封装半导体器件的方法，以及用于组装多个封装的方法，包括用于替代根据本发明的实施例的封装的一个或多个有缺陷的半导体器件的功能的方法。

公开(公告)号：US20110266701A1

公开(公告)日：2011-11-03

申请号：US13182069

申请日：2011-07-13

申请人： Ng Hong Wan ,  Lee Choon Kuan ,  David J. Corisis ,  Chong Chin Hui

发明人： Ng Hong Wan ,  Lee Choon Kuan ,  David J. Corisis ,  Chong Chin Hui

IPC分类号： H01L23/488 ,  H01L21/56

CPC分类号： H01L23/18 ,  H01L21/56 ,  H01L21/565 ,  H01L21/568 ,  H01L21/7806 ,  H01L23/3107 ,  H01L23/373 ,  H01L24/13 ,  H01L24/19 ,  H01L24/95 ,  H01L24/96 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/12105 ,  H01L2924/01029 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00014

摘要： A device is disclosed which includes, in one illustrative example, an integrated circuit die having an active surface and a molded body extending around a perimeter of the die, the molded body having lips that are positioned above a portion of the active surface of the die. Another illustrative example includes an integrated circuit die having an active surface, a molded body extending around a perimeter of the die and a CTE buffer material formed around at least a portion of the perimeter of the die adjacent the active surface of the die, wherein the CTE buffer material is positioned between a portion of the die and a portion of the molded body and wherein the CTE buffer material has a coefficient of thermal expansion that is intermediate a coefficient of thermal expansion for the die and a coefficient of thermal expansion for the molded body.

摘要翻译： 公开了一种在一个说明性示例中包括具有活性表面的集成电路管芯和围绕模具的周边延伸的成型体的模制器件，所述模制体具有位于模具的有效表面的一部分上方的唇缘 。 另一示例性实例包括具有活性表面的集成电路管芯，围绕管芯的周边延伸的成型体和围绕与管芯的有效表面相邻的管芯周边的至少一部分周围形成的CTE缓冲材料，其中， CTE缓冲材料位于模具的一部分和模制体的一部分之间，并且其中CTE缓冲材料的热膨胀系数为模具的热膨胀系数的中间系数和模制的热膨胀系数 身体。

公开(公告)号：US08202754B2

公开(公告)日：2012-06-19

申请号：US11452750

申请日：2006-06-13

申请人： David J. Corisis ,  Chin Hui Chong ,  Choon Kuan Lee

发明人： David J. Corisis ,  Chin Hui Chong ,  Choon Kuan Lee

IPC分类号： H01L21/00

CPC分类号： H01L23/49827 ,  H01L23/24 ,  H01L23/49816 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Packaged microelectronic devices recessed in support member cavities, and associated methods, are disclosed. Method in accordance with one embodiment includes positioning a microelectronic device in a cavity of a support member, with the cavity having a closed end with a conductive layer, and an opening through which the cavity is assessable. The microelectronic device can have bond sites, a first surface, and a second surface facing opposite from the first surface. The microelectronic device can be positioned in the cavity so that the second surface faces toward and is carried by the conductive layer. The method can further include electrically coupling the bond sites of the microelectronic device to the conductive layer. In particular embodiments, the microelectronic device can be encapsulated in the cavity without the need for a releasable tape layer to temporarily support the microelectronic device.

摘要翻译： 封装在支撑构件空腔中的微电子器件以及相关方法被公开。 根据一个实施例的方法包括将微电子器件定位在支撑构件的空腔中，其中空腔具有带有导电层的封闭端以及空腔可以评估的开口。 微电子器件可以具有接合位置，第一表面和与第一表面相对的第二表面。 微电子器件可以定位在空腔中，使得第二表面面向导电层并由导电层承载。 该方法还可以包括将微电子器件的键合位置电耦合到导电层。 在具体实施例中，微电子器件可以被封装在空腔中，而不需要可释放的带层来临时支撑微电子器件。

公开(公告)号：US20120146239A1

公开(公告)日：2012-06-14

申请号：US13399659

申请日：2012-02-17

申请人： David J. Corisis ,  Chin Hui Chong ,  Choon Kuan Lee

发明人： David J. Corisis ,  Chin Hui Chong ,  Choon Kuan Lee

IPC分类号： H01L23/48

CPC分类号： H01L23/49827 ,  H01L23/24 ,  H01L23/49816 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Packaged microelectronic devices recessed in support member cavities, and associated methods, are disclosed. Method in accordance with one embodiment includes positioning a microelectronic device in a cavity of a support member, with the cavity having a closed end with a conductive layer, and an opening through which the cavity is assessable. The microelectronic device can have bond sites, a first surface, and a second surface facing opposite from the first surface. The microelectronic device can be positioned in the cavity so that the second surface faces toward and is carried by the conductive layer. The method can further include electrically coupling the bond sites of the microelectronic device to the conductive layer. In particular embodiments, the microelectronic device can be encapsulated in the cavity without the need for a releasable tape layer to temporarily support the microelectronic device.

摘要翻译： 封装在支撑构件空腔中的微电子器件以及相关方法被公开。 根据一个实施例的方法包括将微电子器件定位在支撑构件的空腔中，其中空腔具有带有导电层的封闭端以及空腔可以评估的开口。 微电子器件可以具有接合位置，第一表面和与第一表面相对的第二表面。 微电子器件可以定位在空腔中，使得第二表面面向导电层并由导电层承载。 该方法还可以包括将微电子器件的键合位置电耦合到导电层。 在具体实施例中，微电子器件可以被封装在空腔中，而不需要可释放的带层来临时支撑微电子器件。

公开(公告)号：US08138021B2

公开(公告)日：2012-03-20

申请号：US12838642

申请日：2010-07-19

申请人： David J. Corisis ,  J. Michael Brooks ,  Choon Kuan Lee ,  Chin Hui Chong

发明人： David J. Corisis ,  J. Michael Brooks ,  Choon Kuan Lee ,  Chin Hui Chong

IPC分类号： H01L21/50

CPC分类号： H01L23/5389 ,  H01L23/49827 ,  H01L24/48 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/4824 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1627 ,  H01L2924/181 ,  Y10T29/53183 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Packaged semiconductor components, apparatus for packaging semiconductor devices, methods of packaging semiconductor devices, and methods of manufacturing apparatus for packaging semiconductor devices. One embodiment of an apparatus for packaging semiconductor devices comprises a first board having a front side, a backside, arrays of die contacts, arrays of first backside terminals electrically coupled to the die contacts, arrays of second backside terminals, and a plurality of individual package areas that have an array of the die contacts, an array of the first backside terminals, and an array of the second backside terminals. The apparatus further includes a second board having a first side laminated to the front side of the first board, a second side, openings through the second board aligned with individual package areas that define die cavities, and arrays of front contacts at the second side electrically coupled to the second backside terminals by interconnects extending through the first board and the second board.

摘要翻译： 封装半导体部件，半导体装置的封装装置，半导体装置的封装方法以及半导体装置的封装装置的制造方法。 用于封装半导体器件的装置的一个实施例包括具有正面，背面，芯片触点阵列，电耦合到裸片触点的第一背面端子阵列，第二背面端子阵列和多个单独封装的第一板 具有芯片触点阵列的区域，第一背面端子的阵列和第二背面端子的阵列。 所述设备还包括第二板，其具有层压到所述第一板的前侧的第一侧，第二侧，穿过所述第二板的开口，所述第二板与限定模腔的各个封装区域对准，并且在所述第二侧上的前触点阵列电 通过延伸穿过第一板和第二板的互连件耦合到第二背面端子。

公开(公告)号：US07915726B2

公开(公告)日：2011-03-29

申请号：US11969300

申请日：2008-01-04

申请人： Chin Hui Chong ,  Choon Kuan Lee ,  David J. Corisis

发明人： Chin Hui Chong ,  Choon Kuan Lee ,  David J. Corisis

IPC分类号： H01L21/311

CPC分类号： H01L23/49816 ,  H01L23/13 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/49109 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012

摘要： Substrates for mounting microelectronic dies, methods for forming vias in such substrates, and methods for packaging microelectronic devices are disclosed herein. A method of manufacturing a substrate in accordance with one embodiment of the invention includes forming a conductive trace on a first side of a sheet of non-conductive material, and forming a via through the non-conductive material from a second side of the sheet to the conductive trace. The method further includes removing a section of the non-conductive material to form an edge of the non-conductive material extending across at least a portion of the via. In one embodiment, forming the edge across the via exposes at least a portion of the second conductive trace for subsequent attachment to a terminal on a microelectronic die.

摘要翻译： 用于安装微电子管芯的基板，在这种基板中形成通孔的方法，以及用于封装微电子器件的方法。 根据本发明的一个实施例的制造基板的方法包括在非导电材料片的第一侧上形成导电迹线，并且从片材的第二面通过非导电材料形成通孔， 导电迹线。 该方法还包括去除非导电材料的一部分以形成穿过通孔的至少一部分延伸的非导电材料的边缘。 在一个实施例中，跨过通孔形成边缘暴露出第二导电迹线的至少一部分，以便随后连接到微电子管芯上的端子。

公开(公告)号：US20100173454A1

公开(公告)日：2010-07-08

申请号：US12726130

申请日：2010-03-17

申请人： Chin Hui Chong ,  Choon Kuan Lee ,  David J. Corisis

发明人： Chin Hui Chong ,  Choon Kuan Lee ,  David J. Corisis

IPC分类号： H01L21/60

CPC分类号： H01L23/4951 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/4952 ,  H01L23/49833 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/16145 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/49171 ,  H01L2224/73207 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06558 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15184 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  Y10T29/49002 ,  Y10T29/49117 ,  Y10T29/49128 ,  Y10T29/49146 ,  Y10T29/49169 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Microelectronic packages with leadframes, including leadframes configured for stacked die packages, and associated systems and methods are disclosed. A system in accordance with one embodiment includes a support member having first package bond sites electrically coupled to leadframe bond sites. A microelectronic die can be carried by the support member and electrically coupled to the first packaged bond sites. A leadframe can be attached to the leadframe bond sites so as to extend adjacent to the microelectronic die, with the die positioned between the leadframe and the support member. The leadframe can include second package bond sites facing away from the first package bond sites. An encapsulant can at least partially surround the leadframe and the microelectronic die, with the first and second package bond sites accessible from outside the encapsulant.

摘要翻译： 公开了具有引线框架的微电子封装，包括配置用于堆叠管芯封装的引线框架，以及相关系统和方法。 根据一个实施例的系统包括具有电耦合到引线框架键合位置的第一封装焊接位置的支撑构件。 微电子管芯可以由支撑构件承载并电耦合到第一封装的粘结位置。 引线框架可以附接到引线框架结合位置，以便在裸片定位在引线框架和支撑构件之间的同时延伸到微电子模具附近。 引线框架可以包括背离第一封装焊接位置的第二封装焊接位置。 密封剂可以至少部分地围绕引线框架和微电子管芯，其中第一和第二封装结合位置可从密封剂外部接近。