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    DUAL SHALLOW TRENCH ISOLATION STRUCTURE
    2.
    发明申请
    DUAL SHALLOW TRENCH ISOLATION STRUCTURE 审中-公开
    双层隔离隔离结构

    公开(公告)号：US20090072355A1

    公开(公告)日：2009-03-19

    申请号：US11856260

    申请日：2007-09-17

    申请人： Kangguo Cheng ,  Lisa F. Edge ,  Johnathan E. Faltermeier ,  Naoyoshi Kusaba

    发明人： Kangguo Cheng ,  Lisa F. Edge ,  Johnathan E. Faltermeier ,  Naoyoshi Kusaba

    IPC分类号： H01L29/06 ,  H01L21/311

    CPC分类号： H01L21/76229 ,  H01L21/76232

    摘要： A protective dielectric layer is formed on a first shallow trench having straight sidewalls, while exposing a second shallow trench. An oxidation barrier layer is formed on the semiconductor substrate. A resist is applied and recessed within the second shallow trench. The oxidation barrier layer is removed above the recessed resist. The resist is removed and thermal oxidation is performed so that a thermal oxide collar is formed above the remaining oxidation mask layer. The oxidation barrier layer is thereafter removed and exposed semiconductor area therebelow depth is etched to form a bottle shaped shallow trench. The first and the bottle shaped trenches are filled with a dielectric material to form a straight sidewall shallow trench isolation structure and a bottle shallow trench isolation structure, respectively. Both shallow trench isolation structures may be employed to provide optimal electrical isolation and device performance to semiconductor devices having different depths.

    摘要翻译： 在具有直的侧壁的第一浅沟槽上形成保护电介质层，同时暴露第二浅沟槽。 在半导体衬底上形成氧化阻挡层。 抗蚀剂被施加并凹入第二浅沟槽内。 在凹陷的抗蚀剂上方去除氧化阻挡层。 去除抗蚀剂并进行热氧化，使得在剩余的氧化掩模层上方形成热氧化物环。 之后除去氧化阻挡层，并对其下方的暴露的半导体区域进行蚀刻以形成瓶状浅沟槽。 第一和瓶形沟槽填充有电介质材料，分别形成直的侧壁浅沟槽隔离结构和瓶浅沟槽隔离结构。 可以使用浅沟槽隔离结构来为具有不同深度的半导体器件提供最佳的电隔离和器件性能。

    Array and moat isolation structures and method of manufacture
    3.
    发明授权
    Array and moat isolation structures and method of manufacture 有权
    阵列和护城隔离结构及其制造方法

    公开(公告)号：US08673737B2

    公开(公告)日：2014-03-18

    申请号：US13274389

    申请日：2011-10-17

    申请人： Naoyoshi Kusaba ,  Oh-jung Kwon ,  Zhengwen Li ,  Hongwen Yan

    发明人： Naoyoshi Kusaba ,  Oh-jung Kwon ,  Zhengwen Li ,  Hongwen Yan

    IPC分类号： H01L21/76

    CPC分类号： H01L29/423 ,  H01L21/762 ,  H01L27/10805 ,  H01L27/10829 ,  H01L27/1087 ,  H01L29/66181 ,  H01L29/945

    摘要： An array or moat isolation structure for eDRAM and methods of manufacture is provided. The method includes forming a deep trench for a memory array and an isolation region. The method includes forming a node dielectric on exposed surfaces of the deep trench for the memory array and the isolation region. The method includes filling remaining portions of the deep trench for the memory array with a metal, and lining the deep trench of the isolation region with the metal. The method includes filling remaining portions of the deep trench for the isolation region with a material, on the metal within the deep trench for the memory array. The method includes recessing the metal within the deep trench for the memory array and the isolation region. The metal in the deep trench of the memory array is recessed to a greater depth than the metal in the isolation region.

    摘要翻译： 提供了一种用于eDRAM的阵列或护城隔离结构及其制造方法。 该方法包括形成用于存储器阵列的深沟槽和隔离区域。 该方法包括在用于存储器阵列和隔离区域的深沟槽的暴露表面上形成节点电介质。 该方法包括用金属填充用于存储器阵列的深沟槽的剩余部分，并用金属衬里隔离区域的深沟槽。 该方法包括用用于存储器阵列的深沟槽内的金属上的材料填充用于隔离区域的深沟槽的剩余部分。 该方法包括使用于存储器阵列和隔离区域的深沟槽内的金属凹陷。 存储器阵列的深沟槽中的金属凹陷到比隔离区域中的金属更深的深度。

    Structure and method of forming enhanced array device isolation for implanted plate eDRAM
    6.
    发明授权
    Structure and method of forming enhanced array device isolation for implanted plate eDRAM 有权
    为植入板eDRAM形成增强阵列器件隔离的结构和方法

    公开(公告)号：US08298907B2

    公开(公告)日：2012-10-30

    申请号：US13323033

    申请日：2011-12-12

    申请人： Herbert L. Ho ,  Naoyoshi Kusaba ,  Karen A. Nummy ,  Carl J. Radens ,  Ravi M. Todi ,  Geng Wang

    发明人： Herbert L. Ho ,  Naoyoshi Kusaba ,  Karen A. Nummy ,  Carl J. Radens ,  Ravi M. Todi ,  Geng Wang

    IPC分类号： H01L21/20

    CPC分类号： H01L27/10823 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/10829 ,  H01L27/1087 ,  H01L27/10897 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/66181

    摘要： A method for forming a memory device in a semiconductor on insulator substrate is provided, in which a protective oxide that is present on the sidewalls of the trench protects the first semiconductor layer, i.e., SOI layer, of the semiconductor on insulator substrate during bottle etching of the trench. In one embodiment, the protective oxide reduces back channel effects of the transistors to the memory devices in the trench that are formed in the semiconductor on insulator substrate. In another embodiment, a thermal oxidation process increases the thickness of the buried dielectric layer of a bonded semiconductor on insulator substrate by oxidizing the bonded interface between the buried dielectric layer and at least one semiconductor layers of the semiconductor on insulator substrate. The increased thickness of the buried dielectric layer may reduce back channel effects in devices formed on the substrate having trench memory structures.

    摘要翻译： 提供了一种在半导体绝缘体衬底上形成存储器件的方法，其中存在于沟槽的侧壁上的保护氧化物在瓶蚀刻期间保护半导体绝缘体衬底上的第一半导体层即SOI层 的沟槽。 在一个实施例中，保护氧化物减少晶体管对形成在绝缘体上半导体衬底上的沟槽中的存储器件的反向沟道效应。 在另一个实施例中，热氧化工艺通过氧化掩埋介电层和绝缘体上半导体衬底的至少一个半导体层之间的键合界面来增加绝缘体衬底上键合的半导体的掩埋介电层的厚度。 掩埋介电层的增加的厚度可以减少在具有沟槽存储器结构的衬底上形成的器件中的反向沟道效应。

    STRUCTURE AND METHOD OF FORMING ENHANCED ARRAY DEVICE ISOLATION FOR IMPLANTED PLATE EDRAM
    7.
    发明申请
    STRUCTURE AND METHOD OF FORMING ENHANCED ARRAY DEVICE ISOLATION FOR IMPLANTED PLATE EDRAM 有权
    形成增强板阵列隔离装置的结构和方法

    公开(公告)号：US20110042731A1

    公开(公告)日：2011-02-24

    申请号：US12545116

    申请日：2009-08-21

    申请人： Herbert L. Ho ,  Naoyoshi Kusaba ,  Karen A. Nummy ,  Carl J. Radens ,  Ravi M. Todi ,  Geng Wang

    发明人： Herbert L. Ho ,  Naoyoshi Kusaba ,  Karen A. Nummy ,  Carl J. Radens ,  Ravi M. Todi ,  Geng Wang

    IPC分类号： H01L27/108 ,  H01L21/28 ,  H01L21/8242

    CPC分类号： H01L27/10823 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/10829 ,  H01L27/1087 ,  H01L27/10897 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/66181

    摘要： A method for forming a memory device in a semiconductor on insulator substrate is provided, in which a protective oxide that is present on the sidewalls of the trench protects the first semiconductor layer, i.e., SOI layer, of the semiconductor on insulator substrate during bottle etching of the trench. In one embodiment, the protective oxide reduces back channel effects of the transistors to the memory devices in the trench that are formed in the semiconductor on insulator substrate. In another embodiment, a thermal oxidation process increases the thickness of the buried dielectric layer of a bonded semiconductor on insulator substrate by oxidizing the bonded interface between the buried dielectric layer and at least one semiconductor layers of the semiconductor on insulator substrate. The increased thickness of the buried dielectric layer may reduce back channel effects in devices formed on the substrate having trench memory structures.

    摘要翻译： 提供了一种在半导体绝缘体衬底上形成存储器件的方法，其中存在于沟槽的侧壁上的保护氧化物在瓶蚀刻期间保护半导体绝缘体衬底上的第一半导体层即SOI层 的沟槽。 在一个实施例中，保护氧化物减少晶体管对形成在绝缘体上半导体衬底上的沟槽中的存储器件的反向沟道效应。 在另一个实施例中，热氧化工艺通过氧化掩埋介电层和绝缘体上半导体衬底的至少一个半导体层之间的键合界面来增加绝缘体衬底上键合的半导体的掩埋介电层的厚度。 掩埋介电层的增加的厚度可以减少在具有沟槽存储器结构的衬底上形成的器件中的反向沟道效应。

    STRUCTURE AND METHOD OF FORMING ENHANCED ARRAY DEVICE ISOLATION FOR IMPLANTED PLATE EDRAM
    9.
    发明申请
    STRUCTURE AND METHOD OF FORMING ENHANCED ARRAY DEVICE ISOLATION FOR IMPLANTED PLATE EDRAM 有权
    形成增强板阵列隔离装置的结构和方法

    公开(公告)号：US20120083092A1

    公开(公告)日：2012-04-05

    申请号：US13323033

    申请日：2011-12-12

    申请人： Herbert L. Ho ,  Naoyoshi Kusaba ,  Karen A. Nummy ,  Carl J. Radens ,  Ravi M. Todi ,  Geng Wang

    发明人： Herbert L. Ho ,  Naoyoshi Kusaba ,  Karen A. Nummy ,  Carl J. Radens ,  Ravi M. Todi ,  Geng Wang

    IPC分类号： H01L21/02

    CPC分类号： H01L27/10823 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/10829 ,  H01L27/1087 ,  H01L27/10897 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/66181

    摘要： A method for forming a memory device in a semiconductor on insulator substrate is provided, in which a protective oxide that is present on the sidewalls of the trench protects the first semiconductor layer, i.e., SOI layer, of the semiconductor on insulator substrate during bottle etching of the trench. In one embodiment, the protective oxide reduces back channel effects of the transistors to the memory devices in the trench that are formed in the semiconductor on insulator substrate. In another embodiment, a thermal oxidation process increases the thickness of the buried dielectric layer of a bonded semiconductor on insulator substrate by oxidizing the bonded interface between the buried dielectric layer and at least one semiconductor layers of the semiconductor on insulator substrate. The increased thickness of the buried dielectric layer may reduce back channel effects in devices formed on the substrate having trench memory structures.

    摘要翻译： 提供了一种在半导体绝缘体衬底上形成存储器件的方法，其中存在于沟槽的侧壁上的保护氧化物在瓶蚀刻期间保护半导体绝缘体衬底上的第一半导体层即SOI层 的沟槽。 在一个实施例中，保护氧化物减少晶体管对形成在绝缘体上半导体衬底上的沟槽中的存储器件的反向沟道效应。 在另一个实施例中，热氧化工艺通过氧化掩埋介电层和绝缘体上半导体衬底的至少一个半导体层之间的键合界面来增加绝缘体衬底上键合的半导体的掩埋介电层的厚度。 掩埋介电层的增加的厚度可以减少在具有沟槽存储器结构的衬底上形成的器件中的反向沟道效应。