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1.发明授权Superscalar microprocessor including flag operand renaming and forwarding apparatus 失效超标量微处理器包括标志操作数重命名和转发设备公开(公告)号：US5805853A
公开(公告)日：1998-09-08
申请号：US799064
申请日：1997-02-10
Applicant: Scott A. White , David S. Christie , Michael D. Goddard
Inventor： Scott A. White , David S. Christie , Michael D. Goddard
CPC classification number: G06F9/30094 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3855 , G06F9/3857 , G06F9/3863
Abstract: A superscalar microprocessor is provided with a reorder buffer for storing the speculative state of the microprocessor and a register file for storing the real state of the microprocessor. A flags register stores the real state of flags that are updated by flag modifying instructions which are executed by the functional units of the microprocessor. To enhance the performance of the microprocessor with respect to conditional branching instructions, the reorder buffer includes a flag storage area for storing flags that are updated by flag modifying instructions. The flags are renamed to make possible the earlier execution of branch instructions which depend on flag modifying instructions. If a flag is not yet determined, then a flag tag is associated with the flag storage area in place of that flag until the actual flag value is determined. A flag operand bus and a flag tag bus are provided between the flag storage area and the branching functional unit so that the requested flag or flag tags are provided to instructions which are executed in the branching functional unit.
Abstract translation: 超标量微处理器设置有用于存储微处理器的推测状态的重排序缓冲器和用于存储微处理器的实际状态的寄存器文件。 标志寄存器存储由微处理器的功能单元执行的标志修改指令更新的标志的实际状态。 为了提高微处理器相对于条件转移指令的性能，重排序缓冲器包括一个标志存储区域，用于存储通过标志修改指令更新的标志。 这些标志被重命名，以便能够更早地执行依赖于标志修改指令的分支指令。 如果尚未确定标志，则标志标签与标志存储区域相关联，而不是该标志，直到确定了实际标志值。 在标志存储区域和分支功能单元之间提供标志操作数总线和标志标签总线，使得所请求的标志或标志标签被提供给在分支功能单元中执行的指令。
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公开(公告)号：US6035386A
公开(公告)日：2000-03-07
申请号：US37436
申请日：1998-02-10
Applicant: David S. Christie , Scott A. White , Michael D. Goddard
Inventor： David S. Christie , Scott A. White , Michael D. Goddard
CPC classification number: G06F9/382 , G06F9/30149 , G06F9/30152 , G06F9/30174 , G06F9/321 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3863
Abstract: A processor which includes a fetch program counter circuit and an execute program counter circuit is disclosed. The fetch program counter circuit provides less significant program counter value bits in addition to a fetch program counter value. The execute program counter circuit generates an execute program counter value using the less significant program counter value bits. The execute program counter circuit receives a plurality of less significant program counter bit values and selects a single less significant program counter bit value thus generating execute program counter values in a multiple pipeline processor.
Abstract translation: 公开了一种包括获取程序计数器电路和执行程序计数器电路的处理器。 获取程序计数器电路除了获取程序计数器值之外还提供不太重要的程序计数器值位。 执行程序计数器电路使用较不重要的程序计数器值位产生执行程序计数器值。 执行程序计数器电路接收多个不太重要的程序计数器位值，并且选择一个不太重要的程序计数器位值，从而在多流水线处理器中产生执行程序计数器值。
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3.发明授权Superscalar microprocessor including flag operand renaming and forwarding apparatus 失效超标量微处理器包括标志操作数重命名和转发设备
公开(公告)号：US5632023A
公开(公告)日：1997-05-20
申请号：US252029
申请日：1994-06-01
Applicant: Scott A. White , David S. Christie , Michael D. Goddard
Inventor： Scott A. White , David S. Christie , Michael D. Goddard
CPC classification number: G06F9/30094 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3855 , G06F9/3857 , G06F9/3863
Abstract: A superscalar microprocessor is provided with a reorder buffer for storing the speculative state of the microprocessor and a register file for storing the real state of the microprocessor. A flags register stores the real state of flags that are updated by flag modifying instructions which are executed by the functional units of the microprocessor. To enhance the performance of the microprocessor with respect to conditional branching instructions, the reorder buffer includes a flag storage area for storing flags that are updated by flag modifying instructions. The flags are renamed to make possible the earlier execution of branch instructions which depend on flag modifying instructions. If a flag is not yet determined, then a flag tag is associated with the flag storage area in place of that flag until the actual flag value is determined. A flag operand bus and a flag tag bus are provided between the flag storage area and the branching functional unit so that the requested flag or flag tags are provided to instructions which are executed in the branching functional unit.
Abstract translation: 超标量微处理器设置有用于存储微处理器的推测状态的重排序缓冲器和用于存储微处理器的实际状态的寄存器文件。 标志寄存器存储由微处理器的功能单元执行的标志修改指令更新的标志的实际状态。 为了提高微处理器相对于条件转移指令的性能，重排序缓冲器包括一个标志存储区域，用于存储通过标志修改指令更新的标志。 这些标志被重命名，以便能够更早地执行依赖于标志修改指令的分支指令。 如果尚未确定标志，则标志标签与标志存储区域相关联，而不是该标志，直到确定了实际标志值。 在标志存储区域和分支功能单元之间提供标志操作数总线和标志标签总线，使得所请求的标志或标志标签提供给在分支功能单元中执行的指令。
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公开(公告)号：US06351801B1
公开(公告)日：2002-02-26
申请号：US09483493
申请日：2000-01-14
Applicant: David S. Christie , Scott A. White , Michael D. Goddard
Inventor： David S. Christie , Scott A. White , Michael D. Goddard
IPC: G06F926
CPC classification number: G06F9/382 , G06F9/30149 , G06F9/30152 , G06F9/30174 , G06F9/321 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3863
Abstract: In a microprocessor system, a program counter circuit generates a program counter value that represents a retrieved instruction and that includes a more significant portion, a less significant portion, and a carry signal for use in determining a next program counter value. An execute program counter circuit generates an execute program counter value from the less significant program counter value and from the carry signal. The execute program counter value represents a program counter value of an executed instruction.
Abstract translation: 在微处理器系统中，程序计数器电路产生表示检索到的指令的程序计数器值，并且包括用于确定下一个程序计数器值的更重要部分，较小有效部分和进位信号。 执行程序计数器电路从较不重要的程序计数器值和进位信号产生执行程序计数器值。 执行程序计数器值表示执行指令的程序计数器值。
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公开(公告)号：US5799162A
公开(公告)日：1998-08-25
申请号：US716764
申请日：1996-09-23
Applicant: David S. Christie , Scott A. White , Michael D. Goddard
Inventor： David S. Christie , Scott A. White , Michael D. Goddard
CPC classification number: G06F9/382 , G06F9/30149 , G06F9/30152 , G06F9/30174 , G06F9/321 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3863
Abstract: A processor which includes a fetch program counter circuit and an execute program counter circuit is disclosed. The fetch program counter circuit provides less significant program counter value bits in addition to a fetch program counter value. The execute program counter circuit generates an execute program counter value using the less significant program counter value bits. The execute program counter circuit receives a plurality of less significant program counter bit values and selects a single less significant program counter bit value thus generating execute program counter values in a multiple pipeline processor.
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公开(公告)号：US5559975A
公开(公告)日：1996-09-24
申请号：US252030
申请日：1994-06-01
Applicant: David S. Christie , Scott A. White , Michael D. Goddard
Inventor： David S. Christie , Scott A. White , Michael D. Goddard
CPC classification number: G06F9/382 , G06F9/30149 , G06F9/30152 , G06F9/30174 , G06F9/321 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3863
Abstract: A processor which includes a fetch program counter circuit and an execute program counter circuit is disclosed. The fetch program counter circuit provides less significant program counter value bits in addition to a fetch program counter value. The execute program counter circuit generates an execute program counter value using the less significant program counter value bits. The execute program counter circuit receives a plurality of less significant program counter bit values and selects a single less significant program counter bit value thus generating execute program counter values in a multiple pipeline processor.
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公开(公告)号：US5857089A
公开(公告)日：1999-01-05
申请号：US967950
申请日：1997-11-12
Applicant: Michael D. Goddard , Scott A. White
Inventor： Michael D. Goddard , Scott A. White
CPC classification number: G06F7/785 , G06F9/30032 , G06F9/3004 , G06F9/30112 , G06F9/30134 , G06F9/3806 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3844 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3885
Abstract: In a processor (110) that performs multiple instructions in a single cycle, predicts outcomes of branch conditions and speculatively executes instructions based on the branch predictions, a method and apparatus for operating a data stack utilize a remap array (674) to support a stack exchange capability. The remap array is used to correlate a stack pointer (672) to data elements (700) within the stack. A lookahead stack pointer (502) and remap array (504) are updated to preserve the processor's state of operation while speculative instructions are executed.
Abstract translation: 在单个周期中执行多个指令的处理器（110）中，预测分支条件的结果并基于分支预测推测地执行指令，用于操作数据堆栈的方法和装置利用重映射阵列（674）来支持堆栈 交换能力。 重映射数组用于将堆栈指针（672）与堆栈内的数据元素（700）相关联。 更新前瞻堆栈指针（502）和重新映射数组（504）以在执行推测性指令时保持处理器的操作状态。
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公开(公告)号：US5737629A
公开(公告)日：1998-04-07
申请号：US671439
申请日：1996-06-27
Applicant: Gerald D. Zuraski, Jr. , Scott A. White , Murali S. Chinnakonda , David S. Christie
Inventor： Gerald D. Zuraski, Jr. , Scott A. White , Murali S. Chinnakonda , David S. Christie
CPC classification number: G06F9/30043 , G06F9/30014 , G06F9/30036 , G06F9/30112 , G06F9/30192 , G06F9/3824 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857
Abstract: A pipelined or superscalar processor (10) that executes operations utilizing operand data of variable bit widths improves parallel performance by partitioning a fixed bit width operand (200) into several partial operand fields (215, 216 and 217), and checking for data dependencies, tagging and forwarding data in these fields independently of one another. An instruction decoder (18) concurrently dispatches multiple ROPs to various functional units (20, 21, 22 and 80). Conflicts which arise with respect to register resources are resolved through register renaming. However, implementation of register renaming is difficult when register structures are overlapping. The present invention supports independent dependency checking, tagging and forwarding of partial bit fields of a register operand which, in combination, allow renaming of registers. Therefore, the variable width register operand structure greatly assists the processor to resolve data dependencies. Operands are tagged by a reorder buffer (26) and supplied with data when it becomes available without regard for the type of data. This method of dependency resolution supports parallel performance of operations and provides a substantial improvement in overall speed of processing. Thus, the processor promotes parallel processing of operations that act upon overlapping data structures which otherwise resist parallel handling.
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公开(公告)号：US5590352A
公开(公告)日：1996-12-31
申请号：US233567
申请日：1994-04-26
Applicant: Gerald D. Zuraski, Jr. , Scott A. White , Murali S. Chinnakonda , David S. Christie
Inventor： Gerald D. Zuraski, Jr. , Scott A. White , Murali S. Chinnakonda , David S. Christie
CPC classification number: G06F9/30043 , G06F9/30014 , G06F9/30036 , G06F9/30112 , G06F9/30192 , G06F9/3824 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857
Abstract: A pipelined or superscalar processor (10) that executes operations utilizing operand data of variable bit widths improves parallel performance by partitioning a fixed bit width operand (200) into several partial operand fields (215, 216 and 217), and checking for data dependencies, tagging and forwarding data in these fields independently of one another. An instruction decoder (18) concurrently dispatches multiple ROPs to various functional units (20, 21, 22 and 80). Conflicts which arise with respect to register resources are resolved through register renaming. However, implementation of register renaming is difficult when register structures are overlapping. The present invention supports independent dependency checking, tagging and forwarding of partial bit fields of a register operand which, in combination, allow renaming of registers. Therefore, the variable width register operand structure greatly assists the processor to resolve data dependencies. Operands are tagged by a reorder buffer (26) and supplied with data when it becomes available without regard for the type of data. This method of dependency resolution supports parallel performance of operations and provides a substantial improvement in overall speed of processing. Thus, the processor promotes parallel processing of operations that act upon overlapping data structures which otherwise resist parallel handling.
Abstract translation: 使用可变位宽的操作数数据执行操作的流水线或超标量处理器（10）通过将固定位宽操作数（200）划分成几个部分操作数字段（215,216和217）来提高并行性能，并且检查数据依赖性， 在这些字段中标记和转发数据，彼此独立。 指令解码器（18）同时将多个ROP调度到各种功能单元（20,21,22和80）。 通过注册重命名来解决与注册资源有关的冲突。 然而，当寄存器结构重叠时，实现寄存器重命名是困难的。 本发明支持对寄存器操作数的部分位字段的独立依赖性检查，标记和转发，其组合允许寄存器重命名。 因此，可变宽度寄存器操作数结构大大有助于处理器解决数据依赖性。 操作数由重排序缓冲器（26）标记，并在数据可用时提供数据，而不考虑数据类型。 这种依赖关系的方法支持并行的操作性能，并提供整体处理速度的实质性改进。 因此，处理器促进对重叠的数据结构起作用的操作的并行处理，否则其将抵抗并行处理。
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10.发明授权Plural operand buses of intermediate widths coupling to narrower width integer and wider width floating point superscalar processing core 失效中间宽度的多个操作数总线耦合到较窄宽度的整数和宽宽度的浮点超标量处理核心
公开(公告)号：US5903772A
公开(公告)日：1999-05-11
申请号：US920649
申请日：1997-08-15
Applicant: Scott A. White , Michael D. Goddard , William M. Johnson
Inventor： Scott A. White , Michael D. Goddard , William M. Johnson
CPC classification number: G06F9/30014 , G06F9/30025 , G06F9/30036 , G06F9/30094 , G06F9/3814 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3885
Abstract: A processor core for supporting the concurrent execution of mixed integer and floating point operations includes integer functional units (110) utilizing 32-bit operand data and a floating point functional unit (22) utilizing up to 82-bit operand data. Eight operand busses (30, 31) connect to the functional units to furnish operand data, and five result busses (32) are connected to the functional units to return results. The width of the operand busses is 41 bits, which is sufficient to communicate either integer or floating point data. This is done using an instruction decoder (18) to apportion a floating point operation which operates on 82-bit floating point operand data into multiple suboperations each associated with a 41-bit suboperand. The operand busses and result busses have an expanded data-handling dimension from the standard integer data width of 32 bits to 41 bits for handling the floating point operands. The floating point functional unit recombines the suboperand data into 82-bits for execution of the floating point operation, and partitions the 82-bit result for output to the result busses. In addition, the excess capacity of the result busses during integer transfers is used to communicate integer flags.
Abstract translation: 用于支持并行执行混合整数和浮点运算的处理器核心包括利用32位操作数数据的整数功能单元（110）和利用高达82位操作数数据的浮点功能单元（22）。 八个操作数总线（30,31）连接到功能单元以提供操作数据，并且五个结果总线（32）连接到功能单元以返回结果。 操作数总线的宽度为41位，足以传送整数或浮点数据。 这是使用指令解码器（18）来完成的，以将对82位浮点运算数据进行操作的浮点运算分配成与41位子波段相关的多个子波形。 操作数总线和结果总线具有从32位的标准整数数据宽度到41位的扩展数据处理维度，用于处理浮点操作数。 浮点功能单元将小波段数据重新组合为82位，用于执行浮点运算，并将82位结果分割为结果总线。 此外，整数传输期间结果总线的剩余容量用于通信整数标志。
