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公开(公告)号:US06436814B1
公开(公告)日:2002-08-20
申请号:US09718010
申请日:2000-11-21
IPC分类号: H01L214763
CPC分类号: H01L21/76847 , H01L21/76805 , H01L21/76814 , H01L21/76877 , H01L23/5226 , H01L23/53238 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要: An interconnection structure preferably including one or more conductors that have a central region filled with an insulator, and a method of fabricating such an interconnection structure for preferably making an electrical connection to the conductor(s). The method preferably includes the steps of depositing and patterning a first insulator over a substrate to form an aperture opening to the substrate; depositing and polishing a first conductor to leave the first conductor in the aperture; depositing and patterning a second insulator to form an opening through the second insulator and a recess in the aperture; depositing one or more second conductors to line the opening and the recess, and to form a central region of the interconnection structure; depositing a third insulator to at least partially fill the central region; and making an electrical connection to the second conductor(s).
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公开(公告)号:US06653737B2
公开(公告)日:2003-11-25
申请号:US10159181
申请日:2002-05-31
IPC分类号: H01L214763
CPC分类号: H01L21/76847 , H01L21/76805 , H01L21/76814 , H01L21/76877 , H01L23/5226 , H01L23/53238 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要: An interconnection structure preferably including one or more conductors that have a central region filled with an insulator, and a method of fabricating such an interconnection structure for preferably making an electrical connection to the conductor(s). The method preferably includes the steps of depositing and patterning a first insulator over a substrate to form an aperture opening to the substrate; depositing and polishing a first conductor to leave the first conductor in the aperture; depositing and patterning a second insulator to form an opening through the second insulator and a recess in the aperture; depositing one or more second conductors to line the opening and the recess, and to form a central region of the interconnection structure; depositing a third insulator to at least partially fill the central region; and making an electrical connection to the second conductor(s).
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公开(公告)号:US06426558B1
公开(公告)日:2002-07-30
申请号:US09854890
申请日:2001-05-14
申请人: Jonathan Chapple-Sokol , Paul M. Feeney , Robert M. Geffken , David V. Horak , Mark P. Murray , Anthony K. Stamper
发明人: Jonathan Chapple-Sokol , Paul M. Feeney , Robert M. Geffken , David V. Horak , Mark P. Murray , Anthony K. Stamper
IPC分类号: H01L2348
CPC分类号: H01L23/485 , H01L21/76807 , H01L21/76849 , H01L21/76883 , H01L21/76885 , H01L21/76895 , H01L21/76897 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要: A method and structure is described which improves the manufacturability of integrated circuit interconnect and stud contacts in contact with semiconductor substrates and upper levels of metallization. The monolithic structure is formed from a thick layer of refractory metal. A variation in the monolithic structure is in the use of a dual damascene local interconnect portion of the structure which allows the local interconnect to pass over structures previously formed on the substrate.
摘要翻译: 描述了一种方法和结构,其改进了与半导体衬底接触的集成电路互连和螺柱触头的可制造性以及较高级别的金属化。 整体结构由难熔金属的厚层形成。 整体结构的变化是使用结构的双镶嵌局部互连部分,其允许局部互连通过先前形成在衬底上的结构。
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公开(公告)号:US06674168B1
公开(公告)日:2004-01-06
申请号:US10248452
申请日:2003-01-21
申请人: Edward C. Cooney, III , Robert M Geffken , Vincent J McGahay , William T. Motsiff , Mark P. Murray , Amanda L. Piper , Anthony K. Stamper , David C. Thomas , Christy S. Tyberg , Elizabeth T. Webster
发明人: Edward C. Cooney, III , Robert M Geffken , Vincent J McGahay , William T. Motsiff , Mark P. Murray , Amanda L. Piper , Anthony K. Stamper , David C. Thomas , Christy S. Tyberg , Elizabeth T. Webster
IPC分类号: H01L2100
CPC分类号: H01L21/76808 , H01L21/76801 , H01L21/76807 , H01L21/76892 , H01L23/525 , H01L23/5329 , H01L23/53295 , H01L2221/1031 , H01L2924/0002 , H01L2924/00
摘要: A method of reworking BEOL (back end of a processing line) metallization levels of damascene metallurgy comprises forming a plurality of BEOL metallization levels over a substrate, forming line and via portions in the BEOL metallization levels, selectively removing at least one of the BEOL metallization levels to expose the line and via portions, and replacing the removed BEOL metallization levels with at least one new BEOL metallization level, wherein the BEOL metallization levels comprise a first dielectric layer and a second dielectric layer, and wherein the first dielectric layer comprising a lower dielectric constant material than the second dielectric layer.
摘要翻译: 一种重新加工BEOL(处理线的后端)金刚石冶金的金属化水平的方法包括在衬底上形成多个BEOL金属化水平,在BEOL金属化水平中形成线和通孔部分,选择性地去除BEOL金属化中的至少一个 以暴露线路和通孔部分,并且用至少一个新的BEOL金属化水平替换去除的BEOL金属化水平,其中BEOL金属化水平包括第一介电层和第二介电层,并且其中第一介电层包括下部 介电常数材料比第二介电层。
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公开(公告)号:US06982227B2
公开(公告)日:2006-01-03
申请号:US10687294
申请日:2003-10-16
申请人: Edward C. Cooney, III , Robert M. Geffken , Vincent J. McGahay , William T. Motsiff , Mark P. Murray , Amanda L. Piper , Anthony K. Stamper , David C. Thomas , Christy S. Tyberg , Elizabeth T. Webster
发明人: Edward C. Cooney, III , Robert M. Geffken , Vincent J. McGahay , William T. Motsiff , Mark P. Murray , Amanda L. Piper , Anthony K. Stamper , David C. Thomas , Christy S. Tyberg , Elizabeth T. Webster
IPC分类号: H01L21/302
CPC分类号: H01L21/76808 , H01L21/76801 , H01L21/76807 , H01L21/76892 , H01L23/525 , H01L23/5329 , H01L23/53295 , H01L2221/1031 , H01L2924/0002 , H01L2924/00
摘要: A method of reworking BEOL (back end of a processing line) metallization levels of damascene metallurgy comprises forming a plurality of BEOL metallization levels over a substrate, forming line and via portions in the BEOL metallization levels, selectively removing at least one of the BEOL metallization levels to expose the line and via portions, and replacing the removed BEOL metallization levels with at least one new BEOL metallization level, wherein the BEOL metallization levels comprise a first dielectric layer and a second dielectric layer, and wherein the first dielectric layer comprising a lower dielectric constant material than the second dielectric layer.
摘要翻译: 一种重新加工BEOL(处理线的后端)金刚石冶金的金属化水平的方法包括在衬底上形成多个BEOL金属化水平,在BEOL金属化水平中形成线和通孔部分,选择性地去除BEOL金属化中的至少一个 以暴露线路和通孔部分,并且用至少一个新的BEOL金属化水平替换去除的BEOL金属化水平,其中BEOL金属化水平包括第一介电层和第二介电层,并且其中第一介电层包括下部 介电常数材料比第二介电层。
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公开(公告)号:US07052625B2
公开(公告)日:2006-05-30
申请号:US09819787
申请日:2001-03-28
IPC分类号: B44C1/22
CPC分类号: C09G1/02 , C09K3/1463 , H01L21/31053 , H01L21/3212
摘要: A slurry containing abrasive particles, an oxidizing agent having a low static etch rate on at least one acid or salt metal, and having a pH of about 5 to about 11 is especially useful for polishing surfaces, including both metal and silicon dioxide, such as present in microelectronics, at the same or substantially the same polishing rates.
摘要翻译: 含有研磨颗粒的淤浆,在至少一种酸或盐金属上具有低静态蚀刻速率并且具有约5至约11的pH的氧化剂特别适用于抛光表面,包括金属和二氧化硅,例如 以相同或基本上相同的抛光速率存在于微电子中。
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7.
公开(公告)号:US06221775B1
公开(公告)日:2001-04-24
申请号:US09159699
申请日:1998-09-24
申请人: Thomas G. Ference , William F. Landers , Michael J. MacDonald , Walter E. Mlynko , Mark P. Murray , Kirk D. Peterson
发明人: Thomas G. Ference , William F. Landers , Michael J. MacDonald , Walter E. Mlynko , Mark P. Murray , Kirk D. Peterson
IPC分类号: H01L21302
CPC分类号: H01L21/7684 , H01L21/3212
摘要: A process of planarizing the surface of a semiconductor substrate. The process begins by forming patterned raised and recessed regions on the surface of the semiconductor substrate. A layer of material then is formed over the patterned raised and recessed regions. The layer is subjected to a chemical mechanical planarizing (CMP) process step until all of the raised regions are at least partially removed from the layer. Finally, the surface of the polished substrate is etched with a reactive ion etching (RIE) process.
摘要翻译: 平面化半导体衬底的表面的工艺。 该过程通过在半导体衬底的表面上形成图案化的凸起和凹陷区域开始。 然后在图案化的凸起和凹陷区域上形成一层材料。 对该层进行化学机械平坦化(CMP)工艺步骤,直到所有凸起区域至少部分地从层中去除。 最后,用反应离子蚀刻(RIE)工艺蚀刻抛光衬底的表面。
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