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    Chemical mechanical polishing techniques for integrated circuit fabrication
    1.
    发明申请
    Chemical mechanical polishing techniques for integrated circuit fabrication 审中-公开
    用于集成电路制造的化学机械抛光技术

    公开(公告)号：US20070082479A1

    公开(公告)日：2007-04-12

    申请号：US11245677

    申请日：2005-10-06

    申请人： Deenesh Padhi ,  Girish Dixit

    发明人： Deenesh Padhi ,  Girish Dixit

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76843 ,  H01L21/76819 ,  H01L21/7684 ,  H01L22/12 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention provides methods for fabricating horizontal interconnect lines for use in semiconductor wafer fabrication. A dielectric layer is deposited on a dielectric stack having a planarized top surface. The dielectric layer is not planarized at this stage of the process. A pre-planarizing thickness profile of the non-planarized dielectric layer is determined and recorded. An interconnect line trench is then etched through the dielectric layer. A sandwich layer including a conductive Cu diffusion barrier layer and a Cu seed layer is deposited in the trench and on the dielectric layer. A Cu comprising metal is deposited in the sandwich lined trench. A Cu metal overburden is thereby deposited on the section of the sandwich layer that is positioned on the dielectric layer. A first CMP process is used to remove the Cu overburden and the Cu seed layer that is formed in the sandwich layer portion on the dielectric layer. A second CMP process is utilized wherein the pre-planarizing thickness profile is employed to remove the Cu barrier layer from the top surface of the dielectric layer, the second CMP process is then continued by planarizing the dielectric layer to form a substantially uniform flat surface having a substantially uniform thickness which is substantially equal to a predetermined design thickness. The second CMP process thereby results in fabricating a dielectric layer wherein substantially all interconnect lines have a substantially uniform thickness that is substantially equal to the design thickness for the dielectric layer.

    摘要翻译： 本发明提供用于制造用于半导体晶片制造的水平互连线的方法。 介电层沉积在具有平坦化顶表面的电介质叠层上。 在该过程的这个阶段，电介质层不被平坦化。 确定并记录非平面化电介质层的预平面化厚度分布。 然后通过介电层蚀刻互连线沟槽。 包含导电性Cu扩散阻挡层和Cu籽晶层的夹层被沉积在沟槽和电介质层上。 包含金属的Cu沉积在夹层衬里的沟槽中。 因此，在位于电介质层上的夹层的部分上沉积Cu金属覆盖层。 使用第一CMP工艺来去除在电介质层上的夹层结构部分中形成的Cu覆盖层和Cu籽晶层。 使用第二CMP工艺，其中使用预平面化厚度轮廓来从电介质层的顶表面去除Cu阻挡层，然后通过平坦化介电层来继续进行第二CMP工艺以形成基本上均匀的平坦表面，其具有 基本均匀的厚度，其基本上等于预定的设计厚度。 因此，第二CMP工艺导致制造介电层，其中基本上所有的互连线具有基本上等于介电层的设计厚度的基本均匀的厚度。

    Electroless deposition method
    4.
    发明授权
    Electroless deposition method 有权
    无电沉积法

    公开(公告)号：US06899816B2

    公开(公告)日：2005-05-31

    申请号：US10117711

    申请日：2002-04-03

    申请人： Deenesh Padhi ,  Joseph Yahalom ,  Sivakami Ramanathan ,  Chris R. McGuirk ,  Srinivas Gandikota ,  Girish Dixit

    发明人： Deenesh Padhi ,  Joseph Yahalom ,  Sivakami Ramanathan ,  Chris R. McGuirk ,  Srinivas Gandikota ,  Girish Dixit

    IPC分类号： C23C18/18 ,  H01L21/285 ,  H01L21/288 ,  H01L21/336 ,  H01L21/768 ,  B44C1/22 ,  B05D3/04 ,  B05D3/10

    CPC分类号： H01L21/76843 ,  C23C18/1651 ,  C23C18/1893 ,  H01L21/28518 ,  H01L21/288 ,  H01L21/76849 ,  H01L21/76874 ,  H01L29/665 ,  H01L2221/1089

    摘要： Methods and apparatus are provided for forming a metal or metal silicide layer by an electroless deposition technique. In one aspect, a method is provided for processing a substrate including depositing an initiation layer on a substrate surface, cleaning the substrate surface, and depositing a conductive material on the initiation layer by exposing the initiation layer to an electroless solution. The method may further comprise etching the substrate surface with an acidic solution and cleaning the substrate of the acidic solution prior to depositing the initiation layer. The initiation layer may be formed by exposing the substrate surface to a noble metal electroless solution or a borane-containing solution. The conductive material may be deposited with a borane-containing reducing agent. The conductive material may be used as a passivation layer, a barrier layer, a seed layer, or for use in forming a metal silicide layer.

    摘要翻译： 提供了通过无电沉积技术形成金属或金属硅化物层的方法和装置。 在一个方面，提供了一种用于处理衬底的方法，包括在衬底表面上沉积起始层，清洁衬底表面，以及通过将引发层暴露于无电镀溶液而在引发层上沉积导电材料。 该方法可以进一步包括用酸性溶液蚀刻衬底表面并在沉积起始层之前清洁酸性溶液的衬底。 起始层可以通过将基材表面暴露于贵金属化学电解溶液或含硼烷溶液来形成。 导电材料可以用含硼烷的还原剂沉积。 导电材料可以用作钝化层，阻挡层，种子层，或用于形成金属硅化物层。

    Nonplanar faceplate for a plasma processing chamber
    6.
    发明授权
    Nonplanar faceplate for a plasma processing chamber 有权
    用于等离子体处理室的非平面面板

    公开(公告)号：US08097082B2

    公开(公告)日：2012-01-17

    申请号：US12110879

    申请日：2008-04-28

    申请人： Jianhua Zhou ,  Deenesh Padhi ,  Karthik Janakiraman ,  Hang Yu ,  Siu F. Cheng ,  Yoganand Saripalli ,  Tersem Summan

    发明人： Jianhua Zhou ,  Deenesh Padhi ,  Karthik Janakiraman ,  Hang Yu ,  Siu F. Cheng ,  Yoganand Saripalli ,  Tersem Summan

    IPC分类号： C23C16/50

    CPC分类号： C23C16/5096 ,  H01J37/32541 ,  Y10T117/10

    摘要： A method and apparatus for adjust local plasma density during a plasma process. One embodiment provides an electrode assembly comprising a conductive faceplate having a nonplanar surface. The nonplanar surface is configured to face a substrate during processing and the conductive faceplate is disposed so that the nonplanar surface is opposing a substrate support having an electrode. The conductive faceplate and the substrate support form a plasma volume. The nonplanar surface is configured to adjust electric field between the conductive plate and the electrode by varying a distance between the conductive plate and the electrode.

    摘要翻译： 一种用于在等离子体工艺期间调节局部等离子体密度的方法和装置。 一个实施例提供了一种电极组件，其包括具有非平面表面的导电面板。 非平面表面被配置为在处理期间面向衬底，并且设置导电面板使得非平面表面与具有电极的衬底支撑件相对。 导电面板和基板支撑件形成等离子体体积。 非平面被配置为通过改变导电板和电极之间的距离来调节导电板和电极之间的电场。

    PLASMA SURFACE TREATMENT TO PREVENT PATTERN COLLAPSE IN IMMERSION LITHOGRAPHY
    9.
    发明申请
    PLASMA SURFACE TREATMENT TO PREVENT PATTERN COLLAPSE IN IMMERSION LITHOGRAPHY 审中-公开
    等离子体表面处理，以防止浸渍图中的图案褶皱

    公开(公告)号：US20090104541A1

    公开(公告)日：2009-04-23

    申请号：US11877559

    申请日：2007-10-23

    申请人： Eui Kyoon Kim ,  Deenesh Padhi ,  Huixiong Dai ,  Mehul Naik ,  Martin Jay Seamons ,  Bok Hoen Kim

    发明人： Eui Kyoon Kim ,  Deenesh Padhi ,  Huixiong Dai ,  Mehul Naik ,  Martin Jay Seamons ,  Bok Hoen Kim

    IPC分类号： G03F1/00

    CPC分类号： G03F7/091 ,  G03F7/11

    摘要： The present invention comprises a method of reducing photoresist mask collapse when the photoresist mask is dried after immersion development. As feature sizes continue to shrink, the capillary force of water used to rinse a photoresist mask approaches the point of being greater than adhesion force of the photoresist to the ARC. When the capillary force exceeds the adhesion force, the features of the mask may collapse because the water pulls adjacent features together as the water dries. By depositing a hermetic oxide layer over the ARC before depositing the photoresist, the adhesion force may exceed the capillary force and the features of the photoresist mask may not collapse.

    摘要翻译： 本发明包括当浸渍显影后干燥光致抗蚀剂掩模时减少光致抗蚀剂掩模塌陷的方法。 随着特征尺寸的不断缩小，用于冲洗光致抗蚀剂掩模的水的毛细管力接近光致抗蚀剂对ARC的粘附力。 当毛细管力超过粘附力时，面具的特征可能会因为水干燥而将相邻的特征拉到一起而崩溃。 通过在沉积光致抗蚀剂之前在ARC上沉积气密的氧化物层，粘合力可能会超过毛细管力，并且光致抗蚀剂掩模的特征可能不会崩溃。