利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

45 条记录 (耗时 0.027 秒)

    Dual layer stress liner for MOSFETS
    1.
    发明授权
    Dual layer stress liner for MOSFETS 失效
    用于MOSFET的双层应力衬垫

    公开(公告)号：US07521308B2

    公开(公告)日：2009-04-21

    申请号：US11616147

    申请日：2006-12-26

    申请人： Deleep R. Nair ,  Christopher V. Baiocco ,  Xiangdong Chen ,  Junjung Kim ,  Jae-eun Park ,  Daewon Yang

    发明人： Deleep R. Nair ,  Christopher V. Baiocco ,  Xiangdong Chen ,  Junjung Kim ,  Jae-eun Park ,  Daewon Yang

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/7843 ,  H01L21/31604 ,  H01L29/66575

    摘要： A method of producing a metal oxide semiconductor field effect transistor (MOSFET) creates a transistor by patterning a gate structure over a substrate, forming spacers on sides of the gate structure, and forming conductor regions within the substrate on alternate sides of the gate stack. The gate structure and the conductor regions make up the transistor. In order to reduce high power plasma induced damage, the method initially applies a first plasma having a first power level to the transistor to form a first stress layer over the transistor. After the first lower-power plasma is applied, the method then applies a second plasma having a second power level to the transistor to from a second stress layer over the first stress layer. The second power level is higher (e.g., at least 5 times higher) than the first power level.

    摘要翻译： 制造金属氧化物半导体场效应晶体管（MOSFET）的方法通过在衬底上图案化栅极结构来形成晶体管，在栅极结构的侧面上形成间隔物，以及在栅极堆叠的另一侧上在衬底内形成导体区域。 栅极结构和导体区域构成晶体管。 为了减少高功率等离子体引起的损伤，该方法首先将具有第一功率电平的第一等离子体施加到晶体管，以在晶体管上形成第一应力层。 在施加第一低功率等离子体之后，该方法然后将第二等离子体具有第二功率电平施加到第一应力层上的第二应力层至晶体管。 第二功率电平比第一功率电平高（例如，至少高5倍）。

    DUAL LAYER STRESS LINER FOR MOSFETS
    2.
    发明申请
    DUAL LAYER STRESS LINER FOR MOSFETS 失效
    用于MOSFET的双层应力衬垫

    公开(公告)号：US20080153217A1

    公开(公告)日：2008-06-26

    申请号：US11616147

    申请日：2006-12-26

    申请人： Deleep R. Nair ,  Christopher V. Baiocco ,  Xiangdong Chen ,  Junjung Kim ,  Jae-eun Park ,  Daewon Yang

    发明人： Deleep R. Nair ,  Christopher V. Baiocco ,  Xiangdong Chen ,  Junjung Kim ,  Jae-eun Park ,  Daewon Yang

    IPC分类号： H01L21/8234 ,  H01L21/336

    CPC分类号： H01L29/7843 ,  H01L21/31604 ,  H01L29/66575

    摘要： A method of producing a metal oxide semiconductor field effect transistor (MOSFET) creates a transistor by patterning a gate structure over a substrate, forming spacers on sides of the gate structure, and forming conductor regions within the substrate on alternate sides of the gate stack. The gate structure and the conductor regions make up the transistor. In order to reduce high power plasma induced damage, the method initially applies a first plasma having a first power level to the transistor to form a first stress layer over the transistor. After the first lower-power plasma is applied, the method then applies a second plasma having a second power level to the transistor to from a second stress layer over the first stress layer. The second power level is higher (e.g., at least 5 times higher) than the first power level.

    摘要翻译： 制造金属氧化物半导体场效应晶体管（MOSFET）的方法通过在衬底上图案化栅极结构来形成晶体管，在栅极结构的侧面上形成间隔物，以及在栅极堆叠的另一侧上在衬底内形成导体区域。 栅极结构和导体区域构成晶体管。 为了减少高功率等离子体引起的损伤，该方法首先将具有第一功率电平的第一等离子体施加到晶体管，以在晶体管上形成第一应力层。 在施加第一低功率等离子体之后，该方法然后将第二等离子体具有第二功率电平施加到第一应力层上的第二应力层至晶体管。 第二功率电平比第一功率电平高（例如，至少高5倍）。

    MODIFICATION OF NITRIDE TOP LAYER
    6.
    发明申请
    MODIFICATION OF NITRIDE TOP LAYER 审中-公开
    硝酸盐层的改性

    公开(公告)号：US20120027956A1

    公开(公告)日：2012-02-02

    申请号：US12846050

    申请日：2010-07-29

    申请人： Daewon Yang ,  Anthony Gene Domenicucci ,  Aurelia Suwarno-Handayana ,  Shamas Musthafa Ummer

    发明人： Daewon Yang ,  Anthony Gene Domenicucci ,  Aurelia Suwarno-Handayana ,  Shamas Musthafa Ummer

    IPC分类号： H05H1/24 ,  C25F3/00

    CPC分类号： C23C16/345 ,  C23C16/52 ,  C23C16/56

    摘要： A method of forming a nitride film is disclosed. In one embodiment, the method comprises performing an ending film deposition process that differs from the main film deposition process in terms of the flow rates of the reactive and ion source gases, and maintaining acceleration power of a CVD tool during the ending film deposition process. A post deposition process may also be used to remove a denser top layer of nitride, resulting in a nitride film having a consistent density.

    摘要翻译： 公开了一种形成氮化物膜的方法。 在一个实施例中，该方法包括执行与主要成膜工艺不同的终止膜沉积工艺，就反应和离子源气体的流量而言，以及在终止膜沉积工艺期间保持CVD工具的加速能力。 后沉积工艺也可用于去除更致密的氮化物顶层，产生具有一致密度的氮化物膜。

    Semiconductor structure
    7.
    发明授权
    Semiconductor structure 失效
    半导体结构

    公开(公告)号：US08030707B2

    公开(公告)日：2011-10-04

    申请号：US12390741

    申请日：2009-02-23

    申请人： Kangguo Cheng ,  Naftali Eliahu Lustig ,  Daewon Yang

    发明人： Kangguo Cheng ,  Naftali Eliahu Lustig ,  Daewon Yang

    IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392

    CPC分类号： H01L21/84 ,  H01L27/10829 ,  H01L27/1087 ,  H01L27/1203

    摘要： A method of forming a silicon-on-insulator (SOI) semiconductor structure in a substrate having a bulk semiconductor layer, a buried oxide (BOX) layer and an SOI layer. During the formation of a trench in the structure, the BOX layer is undercut. The method includes forming a dielectric material on the upper wall of the trench adjacent to the undercutting of the BOX layer and then etching the dielectric material to form a spacer. The spacer fixes the BOX layer undercut and protects it during subsequent steps of forming a bottle-shaped portion of the trench, forming a buried plate in the deep trench; and then forming a trench capacitor. There is also a semiconductor structure, preferably an SOI eDRAM structure, having a spacer which fixes the undercutting in the BOX layer.

    摘要翻译： 一种在具有体半导体层，掩埋氧化物（BOX）层和SOI层的衬底中形成绝缘体上硅（SOI）半导体结构的方法。 在结构中形成沟槽时，BOX层被切削。 该方法包括在邻近BOX层的底切的沟槽的上壁上形成介电材料，然后蚀刻电介质材料以形成间隔物。 间隔件固定BOX层底切并在形成沟槽的瓶形部分的后续步骤期间保护它，在深沟槽中形成掩埋板; 然后形成沟槽电容器。 还存在半导体结构，优选为SOI eDRAM结构，其具有将底切固定在BOX层中的间隔物。

    METHOD FOR FORMING A SEMICONDUCTOR STRUCTURE TO REMEDY BOX UNDERCUT AND STRUCTURE FORMED THEREBY
    8.
    发明申请
    METHOD FOR FORMING A SEMICONDUCTOR STRUCTURE TO REMEDY BOX UNDERCUT AND STRUCTURE FORMED THEREBY 失效
    用于形成半导体结构以获得补偿盒和其结构的方法

    公开(公告)号：US20100213522A1

    公开(公告)日：2010-08-26

    申请号：US12390741

    申请日：2009-02-23

    申请人： Kangguo Cheng ,  Naftali Eliahu Lustig ,  Daewon Yang

    发明人： Kangguo Cheng ,  Naftali Eliahu Lustig ,  Daewon Yang

    IPC分类号： H01L27/108 ,  H01L21/8242

    CPC分类号： H01L21/84 ,  H01L27/10829 ,  H01L27/1087 ,  H01L27/1203

    摘要： A method of forming a silicon-on-insulator (SOI) semiconductor structure in a substrate having a bulk semiconductor layer, a buried oxide (BOX) layer and an SOI layer. During the formation of a trench in the structure, the BOX layer is undercut. The method includes forming a dielectric material on the upper wall of the trench adjacent to the undercutting of the BOX layer and then etching the dielectric material to form a spacer. The spacer fixes the BOX layer undercut and protects it during subsequent steps of forming a bottle-shaped portion of the trench, forming a buried plate in the deep trench; and then forming a trench capacitor. There is also a semiconductor structure, preferably an SOI eDRAM structure, having a spacer which fixes the undercutting in the BOX layer.

    摘要翻译： 一种在具有体半导体层，掩埋氧化物（BOX）层和SOI层的衬底中形成绝缘体上硅（SOI）半导体结构的方法。 在结构中形成沟槽时，BOX层被切削。 该方法包括在邻近BOX层的底切的沟槽的上壁上形成介电材料，然后蚀刻电介质材料以形成间隔物。 间隔件固定BOX层底切并在形成沟槽的瓶形部分的后续步骤期间保护它，在深沟槽中形成掩埋板; 然后形成沟槽电容器。 还存在半导体结构，优选为SOI eDRAM结构，其具有将BOX层中的底切固定的间隔物。

    METHOD AND APPARATUS FOR ANGULAR HIGH DENSITY PLASMA CHEMICAL VAPOR DEPOSITION
    10.
    发明申请
    METHOD AND APPARATUS FOR ANGULAR HIGH DENSITY PLASMA CHEMICAL VAPOR DEPOSITION 有权
    用于高密度等离子体化学蒸气沉积的方法和装置

    公开(公告)号：US20100029082A1

    公开(公告)日：2010-02-04

    申请号：US12185339

    申请日：2008-08-04

    申请人： Daewon Yang ,  Kangguo Cheng ,  Pavel Smetana ,  Richard S. Wise ,  Keith Kwong Hon Wong

    发明人： Daewon Yang ,  Kangguo Cheng ,  Pavel Smetana ,  Richard S. Wise ,  Keith Kwong Hon Wong

    IPC分类号： H01L21/311 ,  C23C16/00

    CPC分类号： C23C16/507 ,  C23C16/345 ,  C23C16/402 ,  C23C16/45578 ,  C23C16/4586 ,  C23C16/56 ,  H01J37/20 ,  H01J37/321 ,  H01J2237/20207 ,  H01J2237/3323 ,  H01L21/31608 ,  H01L21/3185 ,  H01L27/10867

    摘要： Forming a shallow trench capacitor in conjunction with an FET by forming a plurality of STI trenches; for the FET, implanting a first cell well having a first polarity between a first and a second of the STI trenches; for the capacitor, implanting a second cell well having a second polarity in an area of a third of the STI trenches; removing dielectric material from the third STI trench; forming a gate stack having a first portion located between the first and the second of the STI trenches and a second portion located over and extending into the third trench; and performing a source/drain implant of the same polarity as the second cell well, thereby forming a FET in the first cell well, and a capacitor in the second cell well. The second polarity may be opposite from the first polarity. An additional implant may reduce ESR in the second cell well.

    摘要翻译： 通过形成多个STI沟槽与FET结合形成浅沟槽电容器; 对于FET，在第一和第二STI沟槽之间注入具有第一极性的第一单元阱; 对于电容器，在第三个STI沟槽的区域中注入具有第二极性的第二单元阱; 从第三STI沟槽去除电介质材料; 形成具有位于所述STI沟槽的所述第一和第二STI沟槽之间的第一部分和位于所述第三沟槽中并延伸到所述第三沟槽中的第二部分的栅极堆叠; 并且执行与第二单元阱相同极性的源极/漏极注入，从而在第一单元阱中形成FET，以及在第二单元阱中形成电容器。 第二极性可以与第一极性相反。 额外的植入物可以减少第二细胞中的ESR。