公开(公告)号：US5276808A

公开(公告)日：1994-01-04

申请号：US650566

申请日：1991-02-04

申请人： Dennis P. Cheney ,  Robert J. Yagley, Jr. ,  Mark J. Wolski ,  Andrew E. Petruski ,  Josephine A. Boston

发明人： Dennis P. Cheney ,  Robert J. Yagley, Jr. ,  Mark J. Wolski ,  Andrew E. Petruski ,  Josephine A. Boston

IPC分类号： G06F13/38 ,  G06F3/06 ,  G11C7/10 ,  G06F12/02

CPC分类号： G11C7/1048 ,  G11C7/1006

摘要： A system and method for striping data to multiple storage devices is provided. One embodiment of the present invention sequentially gates data to a plurality of buffers, wherein only those buffers corresponding to storage devices in use are induced to gate in data. The data is then sent to the storage devices in parallel. Other embodiments further include the use of striping buffers alternatingly used to gate in data, and transfer data to the storage devices.

摘要翻译： 提供了一种用于将数据分段到多个存储设备的系统和方法。 本发明的一个实施例将数据顺序地将数据门限地存储到多个缓冲器，其中只有对应于使用中的存储装置的那些缓冲器被引导到数据门。 然后将数据并行发送到存储设备。 其他实施例还包括使用交替地用于门控数据的条带化缓冲器，以及将数据传送到存储装置。

公开(公告)号：US5140545A

公开(公告)日：1992-08-18

申请号：US655316

申请日：1991-02-13

申请人： Stamatis Vassiliadis ,  Josephine A. Boston

发明人： Stamatis Vassiliadis ,  Josephine A. Boston

IPC分类号： G06F7/38 ,  G06F7/508 ,  G06F7/52 ,  G06F7/527 ,  G06F7/533 ,  G06F7/535

CPC分类号： G06F7/535 ,  G06F2207/5355

摘要： A system for dividing a digital dividend operand N by a digital divisor operand D to obtain a quotient operand Q with minimal execution time and hardware calculates a value NP.sub.0 P.sub.1 . . . P.sub.m, where the value P.sub.0 P.sub.1 . . . P.sub.m has a magnitude such that NP.sub.0 P.sub.1 . . . P.sub.m converges to Q and DP.sub.0 P.sub.1 converges to 1. The divider employs a one's complementation, multiplication and addition sequence to calculate the value NP.sub.0 P.sub.1 . . . P.sub.m.

公开(公告)号：US5210828A

公开(公告)日：1993-05-11

申请号：US504764

申请日：1990-04-04

申请人： Timothy V. Bolan ,  Josephine A. Boston ,  George A. Fax ,  Donald J. Hanrahan ,  Bernhard Laubli ,  David A. Ring ,  Alfred T. Rundle ,  David J. Shippy

发明人： Timothy V. Bolan ,  Josephine A. Boston ,  George A. Fax ,  Donald J. Hanrahan ,  Bernhard Laubli ,  David A. Ring ,  Alfred T. Rundle ,  David J. Shippy

IPC分类号： G06F15/167

CPC分类号： G06F15/167

摘要： A plurality of processors are connected to the interprocessor communications facility in the multiprocessing system of the invention. The interprocessor communications facility has arbitration circuitry, mailbox circuitry, and processor interrupt circuitry. The interprocessor communications facility of the invention is centralized and does not require the use of main storage. This enables processors to communicate with each other in a fast and efficient manner. The arbitration circuitry prevents simultaneous access of the interprocessor communications facility by more than one processor, and decodes the commands sent from the processors and routes them to the processor interrupt circuitry or to the mailbox circuitry, depending on the command. The mailbox circuitry of the invention receives messages from sending processors and provides them to the intended receiving processors in a safe and secure manner. The processor interrupt circuitry facilitates the interprocessor communications process by handling interprocessor interrupts.

摘要翻译： 多个处理器连接到本发明的多处理系统中的处理器间通信设施。 处理器间通信设施具有仲裁电路，邮箱电路和处理器中断电路。 本发明的处理器间通信设施是集中式的，不需要使用主存储器。 这使得处理器能够以快速和有效的方式相互通信。 仲裁电路防止多个处理器同时访问处理器间通信设施，并根据命令解码从处理器发送的命令并将它们路由到处理器中断电路或邮箱电路。 本发明的邮箱电路从发送处理器接收消息，并以安全和可靠的方式将它们提供给预期的接收处理器。 处理器中断电路通过处理处理器间中断来促进处理器之间的通信过程。