公开(公告)号：US06878611B2

公开(公告)日：2005-04-12

申请号：US10336147

申请日：2003-01-02

申请人： Devendra K. Sadana ,  Stephen W. Bedell ,  Tze-Chiang Chen ,  Kwang Su Choe ,  Keith E. Fogel

发明人： Devendra K. Sadana ,  Stephen W. Bedell ,  Tze-Chiang Chen ,  Kwang Su Choe ,  Keith E. Fogel

IPC分类号： H01L21/76 ,  H01L21/02 ,  H01L21/20 ,  H01L21/324 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/12 ,  H01L21/36

CPC分类号： H01L21/324 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02658 ,  H01L21/02694 ,  H01L21/823807 ,  Y10S438/96

摘要： In the preferred embodiment of this invention a method is described to convert patterned SOI regions into patterned SGOI (silicon-germanium on oxide) by the SiGe/SOI thermal mixing process to further enhance performance of the logic circuit in an embedded DRAM. The SGOI region acts as a template for subsequent Si growth such that the Si is strained, and electron and holes in the Si have higher mobility.

摘要翻译： 在本发明的优选实施例中，描述了通过SiGe / SOI热混合工艺将图案化SOI区域转换为图案化SGOI（氧化硅上的硅 - 锗）的方法，以进一步增强嵌入式DRAM中逻辑电路的性能。 SGOI区域用作随后的Si生长的模板，使得Si被应变，并且Si中的电子和空穴具有较高的迁移率。

公开(公告)号：US07125458B2

公开(公告)日：2006-10-24

申请号：US10662028

申请日：2003-09-12

申请人： Stephen W. Bedell ,  Kwang Su Choe ,  Keith E. Fogel ,  Devendra K. Sadana

发明人： Stephen W. Bedell ,  Kwang Su Choe ,  Keith E. Fogel ,  Devendra K. Sadana

IPC分类号： H01L21/20

CPC分类号： H01L21/76227 ,  C22F1/10 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/76245 ,  H01L29/78603

摘要： A simple and direct method of forming a SiGe-on-insulator that relies on the oxidation of a porous silicon layer (or region) that is created beneath a Ge-containing layer is provided. The method includes the steps of providing a structure comprising a Si-containing substrate having a hole-rich region formed therein and a Ge-containing layer atop the Si-containing substrate; converting the hole-rich region into a porous region; and annealing the structure including the porous region to provide a substantially relaxed SiGe-on-insulator material.

摘要翻译： 提供一种形成依赖于在含Ge层下形成的多孔硅层（或区域）的氧化的绝缘体上硅的简单且直接的方法。 该方法包括以下步骤：提供包括其中形成有富空穴的含Si衬底和含Si衬底顶部的含Ge层的结构; 将富含孔的区域转化为多孔区域; 并退火包括多孔区域的结构，以提供基本上松弛的绝缘体上的SiGe。

公开(公告)号：US07566482B2

公开(公告)日：2009-07-28

申请号：US10674648

申请日：2003-09-30

申请人： Kwang Su Choe ,  Keith E. Fogel ,  Devendra K. Sadana

发明人： Kwang Su Choe ,  Keith E. Fogel ,  Devendra K. Sadana

IPC分类号： C23C14/48 ,  C23C14/08 ,  C23C14/58 ,  H01L21/265 ,  H01L21/316

CPC分类号： H01L21/76245 ,  C25F3/04

摘要： A method in which a SOI substrate structure is fabricated by oxidation of graded porous Si is provided. The graded porous Si is formed by first implanting a dopant (p- or n-type) into a Si-containing substrate, activating the dopant using an activation anneal step and then anodizing the implanted and activated dopant region in a HF-containing solution. The graded porous Si has a relatively coarse top layer and a fine porous layer that is buried beneath the top layer. Upon a subsequent oxidation step, the fine buried porous layer is converted into a buried oxide, while the coarse top layer coalesces into a solid Si-containing over-layer by surface migration of Si atoms.

摘要翻译： 提供了通过分级多孔Si的氧化制造SOI衬底结构的方法。 通过首先将掺杂剂（p型或n型）注入到含Si衬底中，使用激活退火步骤激活掺杂剂，然后对含HF溶液中的注入和活化的掺杂剂区进行阳极化，形成渐变多孔Si。 分级多孔Si具有相对粗糙的顶层和埋在顶层下方的细多孔层。 在随后的氧化步骤中，精细埋入的多孔层被转化为掩埋氧化物，而粗顶层通过Si原子的表面迁移而结合成固体含Si的超层。

公开(公告)号：US06800518B2

公开(公告)日：2004-10-05

申请号：US10334220

申请日：2002-12-30

申请人： Robert E. Bendernagel ,  Kwang Su Choe ,  Bijan Davari ,  Keith E. Fogel ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Sandip Tiwari

发明人： Robert E. Bendernagel ,  Kwang Su Choe ,  Bijan Davari ,  Keith E. Fogel ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Sandip Tiwari

IPC分类号： H01L318234

CPC分类号： H01L21/324 ,  H01L21/76243

摘要： A patterned SOI/SON composite structure and methods of forming the same are provided. In the SOI/SON composite structure, the patterned SOI/SON structures are sandwiched between a Si over-layer and a semiconductor substrate. The method of forming the patterned SOI/SON composite structure includes shared processing steps wherein the SOI and SON structure are formed together. The present invention also provides a method of forming a composite structure which includes buried conductive/SON structures as well as a method of forming a composite structure including only buried void planes.

摘要翻译： 提供了图案化的SOI / SON复合结构及其形成方法。 在SOI / SON复合结构中，图案化SOI / SON结构夹在Si上层和半导体衬底之间。 形成图案化SOI / SON复合结构的方法包括共同的处理步骤，其中SOI和SON结构形成在一起。 本发明还提供一种形成复合结构的方法，该复合结构包括掩埋导电/ SON结构以及形成仅包括掩埋空隙平面的复合结构的方法。

公开(公告)号：US07718231B2

公开(公告)日：2010-05-18

申请号：US10674647

申请日：2003-09-30

申请人： Kwang Su Choe ,  Keith E. Fogel ,  Siegfried L. Maurer ,  Ryan M. Mitchell ,  Devendra K. Sadana

发明人： Kwang Su Choe ,  Keith E. Fogel ,  Siegfried L. Maurer ,  Ryan M. Mitchell ,  Devendra K. Sadana

IPC分类号： C23C14/10 ,  C23C14/48 ,  C23C14/58 ,  H01L21/762

CPC分类号： H01L21/76243 ,  H01L21/26533 ,  H01L21/3063 ,  H01L21/31662

摘要： A method of fabricating silicon-on-insulators (SOIs) having a thin, but uniform buried oxide region beneath a Si-containing over-layer is provided. The SOI structures are fabricated by first modifying a surface of a Si-containing substrate to contain a large concentration of vacancies or voids. Next, a Si-containing layer is typically, but not always, formed atop the substrate and then oxygen ions are implanted into the structure utilizing a low-oxygen dose. The structure is then annealed to convert the implanted oxygen ions into a thin, but uniform thermal buried oxide region.

摘要翻译： 提供了一种制造在含Si的上层下方具有薄而均匀的掩埋氧化物区域的硅绝缘体（SOI）的方法。 通过首先修饰含Si衬底的表面以包含大量的空位或空隙的浓度来制造SOI结构。 接下来，含硅层通常但不总是形成在衬底顶上，然后使用低氧剂量将氧离子注入到结构中。 然后将结构退火以将注入的氧离子转化成薄但均匀的热掩埋氧化物区域。

公开(公告)号：US20130126493A1

公开(公告)日：2013-05-23

申请号：US13302427

申请日：2011-11-22

申请人： Stephen W. Bedell ,  Cheng-Wei Cheng ,  Keith E. Fogel ,  Devendra K. Sadana ,  Katherine L. Saenger ,  Norma E. Sosa Cortes ,  Ning Li ,  Ibrahim Alhomoudi

发明人： Stephen W. Bedell ,  Cheng-Wei Cheng ,  Keith E. Fogel ,  Devendra K. Sadana ,  Katherine L. Saenger ,  Norma E. Sosa Cortes ,  Ning Li ,  Ibrahim Alhomoudi

IPC分类号： B23K26/00

CPC分类号： H01L21/268 ,  B23K26/0624 ,  B23K26/364 ,  B23K26/40 ,  B23K2103/50 ,  H01L21/31127 ,  H01L21/32131 ,  H01L21/6835 ,  H01L2221/68327

摘要： Laser ablation can be used to form a trench within at least a blanket layer of a stressor layer that is atop a base substrate. A non-ablated portion of the stressor layer has an edge that defines the edge of the material layer region to be spalled. Laser ablation can also be used to form a trench within a blanket material stack including at least a plating seed layer. A stressor layer is formed on the non-ablated portions of the material stack and one portion of the stressor layer has an edge that defines the edge of the material layer region to be spalled. Laser ablation can be further used to form a trench that extends through a blanket stressor layer and into the base substrate itself. The trench has an edge that defines the edge of the material layer region to be spalled.

公开(公告)号：US07679141B2

公开(公告)日：2010-03-16

申请号：US12027561

申请日：2008-02-07

申请人： Stephen W. Bedell ,  Huajie Chen ,  Anthony G. Domenicucci ,  Keith E. Fogel ,  Richard J. Murphy ,  Devendra K. Sadana

发明人： Stephen W. Bedell ,  Huajie Chen ,  Anthony G. Domenicucci ,  Keith E. Fogel ,  Richard J. Murphy ,  Devendra K. Sadana

IPC分类号： H01L31/392

CPC分类号： H01L21/26506 ,  H01L21/324 ,  H01L21/7624 ,  H01L21/76254 ,  H01L29/1054

摘要： A method of forming a low-defect, substantially relaxed SiGe-on-insulator substrate material is provided. The method includes first forming a Ge-containing layer on a surface of a first single crystal Si layer which is present atop a barrier layer that is resistant to Ge diffusion. A heating step is then performed at a temperature that approaches the melting point of the final SiGe alloy and retards the formation of stacking fault defects while retaining Ge. The heating step permits interdiffusion of Ge throughout the first single crystal Si layer and the Ge-containing layer thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer. Moreover, because the heating step is carried out at a temperature that approaches the melting point of the final SiGe alloy, defects that persist in the single crystal SiGe layer as a result of relaxation are efficiently annihilated therefrom. In one embodiment, the heating step includes an oxidation process that is performed at a temperature from about 1230° to about 1320° C. for a time period of less than about 2 hours. This embodiment provides SGOI substrate that have minimal surface pitting and reduced crosshatching.

摘要翻译： 提供一种形成低缺陷，基本上松弛的绝缘体上硅衬底材料的方法。 该方法包括首先在耐Ge扩散的阻挡层上存在的第一单晶Si层的表面上形成含Ge层。 然后在接近最终SiGe合金的熔点的温度下进行加热步骤，并且在保留Ge的同时延缓层叠缺陷缺陷的形成。 加热步骤允许Ge遍及第一单晶Si层和含Ge层的相互扩散，从而在阻挡层顶部形成基本松弛的单晶SiGe层。 此外，由于加热步骤在接近最终SiGe合金的熔点的温度下进行，所以由于弛豫而在单晶SiGe层中持续存在的缺陷被有效地湮灭。 在一个实施方案中，加热步骤包括氧化过程，其在约1230℃至约1320℃的温度下进行约少于约2小时的时间。 该实施例提供具有最小表面点蚀和减少的交叉阴影的SGOI衬底。

公开(公告)号：US06989058B2

公开(公告)日：2006-01-24

申请号：US10654232

申请日：2003-09-03

申请人： Stephen W. Bedell ,  Huajie Chen ,  Keith E. Fogel ,  Devendra K. Sadana

发明人： Stephen W. Bedell ,  Huajie Chen ,  Keith E. Fogel ,  Devendra K. Sadana

IPC分类号： C30B25/02

CPC分类号： H01L21/7624 ,  C30B29/52 ,  C30B31/02 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02694 ,  Y10T428/24917

摘要： High-quality, metastable SiGe alloys are formed on SOI substrates having an SOI layer of about 500 Å or less, the SiGe layers can remain substantially fully strained compared to identical SiGe layers formed on thicker SOI substrates and subsequently annealed and/or oxidized at high temperatures. The present invention thus provides a method of ‘frustrating’ metastable strained SiGe layers by growing them on thin, clean and high-quality SOI substrates.

摘要翻译： 在具有大约等于或小于等于或等于SOI层的SOI层的SOI衬底上形成高质量的亚稳态SiGe合金，与形成在较厚SOI衬底上的相同SiGe层相比，SiGe层可以保持基本上完全变形，并随后在高温下退火和/或氧化 温度。 因此，本发明提供了一种通过在薄的，清洁的和高质量的SOI衬底上生长它们来“挫败”亚稳应变的SiGe层的方法。

公开(公告)号：US06841457B2

公开(公告)日：2005-01-11

申请号：US10196611

申请日：2002-07-16

申请人： Stephen W. Bedell ,  Keith E. Fogel ,  Devendra K. Sadana

发明人： Stephen W. Bedell ,  Keith E. Fogel ,  Devendra K. Sadana

IPC分类号： H01L29/161 ,  H01L21/20 ,  H01L21/265 ,  H01L21/762 ,  H01L21/36

CPC分类号： H01L21/76243 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02664 ,  Y10S438/933

摘要： A method of forming a relaxed SiGe-on-insulator substrate having enhanced relaxation, significantly lower defect density and improved surface quality is provided. The method includes forming a SiGe alloy layer on a surface of a first single crystal Si layer. The first single crystal Si layer has an interface with an underlying barrier layer that is resistant to Ge diffusion. Next, ions that are capable of forming defects that allow mechanical decoupling at or near said interface are implanted into the structure and thereafter the structure including the implanted ions is subjected to a heating step which permits interdiffusion of Ge throughout the first single crystal Si layer and the SiGe layer to form a substantially relaxed, single crystal and homogeneous SiGe layer atop the barrier layer. SiGe-on-insulator substrates having the improved properties as well as heterostructures containing the same are also provided.

公开(公告)号：US06803240B1

公开(公告)日：2004-10-12

申请号：US10654231

申请日：2003-09-03

申请人： Stephen W. Bedell ,  Keith E. Fogel ,  Devendra K. Sadana

发明人： Stephen W. Bedell ,  Keith E. Fogel ,  Devendra K. Sadana

IPC分类号： H01L21302

CPC分类号： G01N21/9501 ,  G01N21/9505 ,  G01N2021/8461

摘要： Described herein is a method for delineating crystalline defects in a thin Si layer over a SiGe alloy layer. The method uses a defect etchant with a high-defect selectivity in Si. The Si is etched downed to a thickness that allows the defect pits to reach the underlying SiGe layer. A second etchant, which can be the same or different from the defect etchant, is then used which attacks the SiGe layer under the pits while leaving Si intact.

摘要翻译： 这里描述了一种在SiGe合金层上描绘薄Si层中的晶体缺陷的方法。 该方法在Si中具有高缺陷选择性的缺陷蚀刻剂。 将Si蚀刻到允许缺陷凹坑到达下面的SiGe层的厚度。 然后使用可以与缺陷蚀刻剂相同或不同的第二蚀刻剂，其在凹陷下攻击SiGe层，同时保持Si完整。