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    Method of fabricating a semiconductor device
    1.
    发明授权
    Method of fabricating a semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US07825031B2

    公开(公告)日：2010-11-02

    申请号：US11855809

    申请日：2007-09-14

    申请人： Dirk Manger ,  Rolf Weis ,  Christoph Noelscher

    发明人： Dirk Manger ,  Rolf Weis ,  Christoph Noelscher

    IPC分类号： H01L21/302

    CPC分类号： H01L21/31144 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L21/76816

    摘要： The invention relates to a method of fabricating an integrated circuit, including the steps of providing at least one layer; performing a first implantation step, wherein particles are implanted into the layer under a first direction of incidence; performing a second implantation step, wherein particles are implanted into the layer under a second direction of incidence which is different from the first direction of incidence; performing a removal step, wherein the layer is partially removed depending on the local implant dose generated by the first and the second implantation step.

    摘要翻译： 本发明涉及一种制造集成电路的方法，包括提供至少一层的步骤; 执行第一注入步骤，其中在第一入射方向上将颗粒注入所述层中; 执行第二注入步骤，其中在与所述第一入射方向不同的第二入射方向上将颗粒注入所述层中; 执行去除步骤，其中根据由第一和第二植入步骤产生的局部植入剂量部分去除该层。

    Method of Fabricating a Semiconductor Device
    4.
    发明申请
    Method of Fabricating a Semiconductor Device 有权
    制造半导体器件的方法

    公开(公告)号：US20090075462A1

    公开(公告)日：2009-03-19

    申请号：US11855809

    申请日：2007-09-14

    申请人： Dirk Manger ,  Rolf Weis ,  Christoph Noelscher

    发明人： Dirk Manger ,  Rolf Weis ,  Christoph Noelscher

    IPC分类号： H01L21/425

    CPC分类号： H01L21/31144 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L21/76816

    摘要： The invention relates to a method of fabricating an integrated circuit, including the steps of providing at least one layer; performing a first implantation step, wherein particles are implanted into the layer under a first direction of incidence; performing a second implantation step, wherein particles are implanted into the layer under a second direction of incidence which is different from the first direction of incidence; performing a removal step, wherein the layer is partially removed depending on the local implant dose generated by the first and the second implantation step.

    摘要翻译： 本发明涉及一种制造集成电路的方法，包括提供至少一层的步骤; 执行第一注入步骤，其中在第一入射方向上将颗粒注入所述层中; 执行第二注入步骤，其中在与所述第一入射方向不同的第二入射方向上将颗粒注入所述层中; 执行去除步骤，其中根据由第一和第二植入步骤产生的局部植入剂量部分去除该层。

    Methods of Manufacturing a Semiconductor Device
    5.
    发明申请
    Methods of Manufacturing a Semiconductor Device 审中-公开
    制造半导体器件的方法

    公开(公告)号：US20090239314A1

    公开(公告)日：2009-09-24

    申请号：US12051932

    申请日：2008-03-20

    申请人： Martin Haberjahn ,  Sascha Dieter ,  Andrea Graf ,  Christoph Noelscher ,  Dirk Manger ,  Stephan Wege

    发明人： Martin Haberjahn ,  Sascha Dieter ,  Andrea Graf ,  Christoph Noelscher ,  Dirk Manger ,  Stephan Wege

    IPC分类号： H01L21/66

    CPC分类号： H01L22/12 ,  H01L22/26

    摘要： Methods of manufacturing a semiconductor device and an apparatus for the manufacturing of semiconductor devices are provided. An embodiment regards providing a process which changes the volume of at least one layer of a semiconductor substrate or of at least one layer deposited on the semiconductor substrate, and measuring a change in volume of such at least one layer using fluorescence. In another embodiment, a change in volume of such at least one layer is measured using reflection of electromagnetic waves.

    摘要翻译： 提供制造半导体器件的方法和用于制造半导体器件的设备。 实施例涉及提供一种改变至少一层半导体衬底或沉积在半导体衬底上的至少一层的层的体积，并使用荧光来测量这样的至少一层的体积变化的过程。 在另一个实施例中，使用电磁波的反射来测量这样的至少一层的体积变化。

    DRAM cell array having vertical memory cells and methods for fabricating a DRAM cell array and a DRAM
    6.
    发明申请
    DRAM cell array having vertical memory cells and methods for fabricating a DRAM cell array and a DRAM 审中-公开
    具有垂直存储单元的DRAM单元阵列和用于制造DRAM单元阵列和DRAM的方法

    公开(公告)号：US20050088895A1

    公开(公告)日：2005-04-28

    申请号：US10897687

    申请日：2004-07-23

    申请人： Dirk Manger ,  Till Schloesser ,  Rolf Weis ,  Bernd Goebel ,  Wolfgang Mueller ,  Joachim Nuetzel ,  Klaus Muemmler

    发明人： Dirk Manger ,  Till Schloesser ,  Rolf Weis ,  Bernd Goebel ,  Wolfgang Mueller ,  Joachim Nuetzel ,  Klaus Muemmler

    IPC分类号： G11C11/34

    CPC分类号： H01L27/10841 ,  H01L27/10867

    摘要： Memory cells having a cell capacitor and a cell transistor, which are arranged in a vertical cell structure, are provided in the cell array of a DRAM. By means of a deep implantation or a shallow implantation with subsequent epitaxial growth of silicon, a buried source/drain layer is formed, from which lower source/drain regions of the cell transistors emerge. The upper edge of the buried source/drain layer can be aligned with respect to a lower edge of a gate electrode of the cell transistor, which consequently results in a reduction of a gate/drain capacitance and also a leakage current between the gate electrode and the lower source/drain region. A gate conductor layer structure is applied and there are formed, from the gate conductor layer structure, in a controlled transistor array, gate electrode structures of control transistors and, in the cell array, a body connection structure for the connection of body regions of the cell transistors.

    摘要翻译： 在DRAM的单元阵列中设置具有单元电容器和单元晶体管的存储单元，其被布置在垂直单元结构中。 通过深度注入或随后的硅的外延生长的浅注入，形成掩埋源极/漏极层，电池晶体管的下部源极/漏极区域从该衬底源极/漏极层出现。 掩埋源极/漏极层的上边缘可以相对于单元晶体管的栅电极的下边缘对准，这因此导致栅极/漏​​极电容的减小以及栅电极和漏极电极之间的漏电流 较低的源极/漏极区域。 施加栅极导体层结构，并且从栅极导体层结构形成受控晶体管阵列，控制晶体管的栅极电极结构以及在单元阵列中形成用于连接主体区域的主体连接结构 单元晶体管。

    DRAM cell array and memory cell arrangement having vertical memory cells and methods for fabricating the same
    7.
    发明申请
    DRAM cell array and memory cell arrangement having vertical memory cells and methods for fabricating the same 失效
    具有垂直存储单元的DRAM单元阵列和存储单元布置及其制造方法

    公开(公告)号：US20050083724A1

    公开(公告)日：2005-04-21

    申请号：US10898706

    申请日：2004-07-23

    申请人： Dirk Manger ,  Till Schloesser ,  Rolf Weis ,  Bernd Goebel ,  Wolfgang Mueller

    发明人： Dirk Manger ,  Till Schloesser ,  Rolf Weis ,  Bernd Goebel ,  Wolfgang Mueller

    IPC分类号： G11C11/34 ,  H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10867 ,  H01L27/10841 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/10891

    摘要： Memory cells each having a cell capacitor and a cell transistor, which are arranged in a vertical cell structure, are provided in the cell array of a DRAM. By means of a deep implantation or a shallow implantation and subsequent epitaxial growth of silicon, a buried source/drain layer is formed, from which lower source/drain regions of the cell transistors emerge. The upper edge of the buried source/drain layer can be aligned with respect to a lower edge of a gate electrode of the cell transistor and this results in a reduction of a gate/drain capacitance and also a leakage current between the gate electrode and the lower source/drain region. A body connection plate for the connection of the channel regions is applied to the substrate surface and contact holes are introduced into the body connection plate. Upper source/drain regions of the cell transistors are formed by implantation through the contact holes.

    摘要翻译： 每个具有单元电容器和单元晶体管的存储单元被布置在垂直单元结构中，被提供在DRAM的单元阵列中。 通过深度注入或浅注入和随后的硅的外延生长，形成掩埋源极/漏极层，电池晶体管的下部源极/漏极区域从该衬底源极/漏极层出现。 掩埋源极/漏极层的上边缘可以相对于单元晶体管的栅电极的下边缘对齐，并且这导致栅极/漏​​极电容的减小以及栅电极和漏电极之间的漏电流 较低的源极/漏极区域。 用于连接通道区域的主体连接板被施加到基板表面，并且接触孔被引入主体连接板。 单元晶体管的上源/漏区通过接触孔注入而形成。

    DRAM cell array and memory cell arrangement having vertical memory cells and methods for fabricating the same
    8.
    发明授权
    DRAM cell array and memory cell arrangement having vertical memory cells and methods for fabricating the same 失效
    具有垂直存储单元的DRAM单元阵列和存储单元布置及其制造方法

    公开(公告)号：US07141845B2

    公开(公告)日：2006-11-28

    申请号：US10898706

    申请日：2004-07-23

    申请人： Dirk Manger ,  Till Schloesser ,  Rolf Weis ,  Bernd Goebel ,  Wolfgang Mueller

    发明人： Dirk Manger ,  Till Schloesser ,  Rolf Weis ,  Bernd Goebel ,  Wolfgang Mueller

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10867 ,  H01L27/10841 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/10891

    摘要： Memory cells each having a cell capacitor and a cell transistor, which are arranged in a vertical cell structure, are provided in the cell array of a DRAM. By means of a deep implantation or a shallow implantation and subsequent epitaxial growth of silicon, a buried source/drain layer is formed, from which lower source/drain regions of the cell transistors emerge. The upper edge of the buried source/drain layer can be aligned with respect to a lower edge of a gate electrode of the cell transistor and this results in a reduction of a gate/drain capacitance and also a leakage current between the gate electrode and the lower source/drain region. A body connection plate for the connection of the channel regions is applied to the substrate surface and contact holes are introduced into the body connection plate. Upper source/drain regions of the cell transistors are formed by implantation through the contact holes.

    摘要翻译： 每个具有单元电容器和单元晶体管的存储单元被布置在垂直单元结构中，被提供在DRAM的单元阵列中。 通过深度注入或浅注入和随后的硅的外延生长，形成掩埋源极/漏极层，电池晶体管的下部源极/漏极区域从该衬底源极/漏极层出现。 掩埋源极/漏极层的上边缘可以相对于单元晶体管的栅电极的下边缘对齐，并且这导致栅极/漏​​极电容的减小以及栅电极和漏电极之间的漏电流 较低的源极/漏极区域。 用于连接通道区域的主体连接板被施加到基板表面，并且接触孔被引入主体连接板。 单元晶体管的上源/漏区通过接触孔注入而形成。