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公开(公告)号：US06946898B1
公开(公告)日：2005-09-20
申请号：US10810039
申请日：2004-03-26
摘要： A bias system is disclosed including a calibration bus to which a controller, a reference bias source, a master bias source, and first and second slave bias sources are coupled. The controller varies a control code sent over the calibration bus to the master bias source until a particular control code is found that causes the bias signal of the master bias source to equal a desired bias value which is provided by the reference bias source. The controller then sends the particular control code to the first and second slave bias sources to cause the first and second slave bias sources to generate a bias signal having the same desired bias value as the master bias source. Isolation between load circuits coupled to the first and second bias sources is thus enhanced while providing low noise, stable operation.
摘要翻译： 公开了一种偏置系统，其包括校准总线，控制器，参考偏置源，主偏置源以及第一和第二从属偏置源耦合到校准总线。 控制器将通过校准总线发送的控制代码改变为主偏置源，直到找到导致主偏置源的偏置信号等于由参考偏置源提供的期望偏置值的特定控制代码。 然后，控制器将特定控制码发送到第一和第二从属偏置源，以使第一和第二从属偏置源产生具有与主偏置源相同的期望偏置值的偏置信号。 因此，耦合到第一和第二偏置源的负载电路之间的隔离增强，同时提供低噪声，稳定的操作。
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公开(公告)号：US20050212585A1
公开(公告)日：2005-09-29
申请号：US10810039
申请日：2004-03-26
申请人： Donald Kerth , Augusto Marques , Dylan Hester , Russell Croman
发明人： Donald Kerth , Augusto Marques , Dylan Hester , Russell Croman
摘要： A bias system is disclosed including a calibration bus to which a controller, a reference bias source, a master bias source, and first and second slave bias sources are coupled. The controller varies a control code sent over the calibration bus to the master bias source until a particular control code is found that causes the bias signal of the master bias source to equal a desired bias value which is provided by the reference bias source. The controller then sends the particular control code to the first and second slave bias sources to cause the first and second slave bias sources to generate a bias signal having the same desired bias value as the master bias source. Isolation between load circuits coupled to the first and second bias sources is thus enhanced while providing low noise, stable operation
摘要翻译： 公开了一种偏置系统，其包括校准总线，控制器，参考偏置源，主偏置源以及第一和第二从属偏置源耦合到校准总线。 控制器将通过校准总线发送的控制代码改变为主偏置源，直到找到导致主偏置源的偏置信号等于由参考偏置源提供的期望偏置值的特定控制代码。 然后，控制器将特定控制码发送到第一和第二从属偏置源，以使第一和第二从属偏置源产生具有与主偏置源相同的期望偏置值的偏置信号。 因此，耦合到第一和第二偏置源的负载电路之间的隔离增强，同时提供低噪声，稳定的操作
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公开(公告)号：US07882282B2
公开(公告)日：2011-02-01
申请号：US12154265
申请日：2008-05-21
申请人： Scott Haban , Dylan Hester , Ruifeng Sun
发明人： Scott Haban , Dylan Hester , Ruifeng Sun
CPC分类号： G06F13/4282
摘要： A demodulator can include first data and clock pads to couple the demodulator to a host device via a first bus, and second data and clock pads to couple the demodulator to a radio frequency (RF) tuner via a second bus. The device may further include passthrough logic to couple host data and a host clock from the first bus to the second bus and to couple tuner data from the second bus to the first bus during a passthrough mode. During this mode, however, the two buses may remain electrically decoupled. When the passthrough mode is disabled, the RF tuner is thus shielded from noise present on the first bus.
摘要翻译： 解调器可以包括经由第一总线将解调器耦合到主机设备的第一数据和时钟焊盘，以及经由第二总线将解调器耦合到射频（RF）调谐器的第二数据和时钟焊盘。 该设备还可以包括用于将主机数据和主机时钟从第一总线耦合到第二总线的通过逻辑，并且在直通模式期间将调谐器数据从第二总线耦合到第一总线。 然而，在这种模式下，两条总线可能保持电气分离。 当禁用直通模式时，RF调谐器被屏蔽，避免了第一个总线上存在的噪声。
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公开(公告)号：US20060068744A1
公开(公告)日：2006-03-30
申请号：US11112153
申请日：2005-04-22
申请人： James Maligeorgos , Dylan Hester , Augusto Marques , G. Tuttle
发明人： James Maligeorgos , Dylan Hester , Augusto Marques , G. Tuttle
CPC分类号： H03L7/00
摘要： A technique includes selectively coupling impedances to an oscillator to establish a first frequency of operation of the oscillator. The technique includes repeating the selective coupling in a feedback loop to cause the first frequency to be near a second frequency.
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5.发明授权
公开(公告)号：US6011501A
公开(公告)日：2000-01-04
申请号：US224389
申请日：1998-12-31
申请人： Xue-Mei Gong , John James Paulos , Mark Alexander , Eric Gaalaas , Dylan Hester
发明人： Xue-Mei Gong , John James Paulos , Mark Alexander , Eric Gaalaas , Dylan Hester
摘要： Digital-to-analog conversion circuitry 100 is shown including a path for processing data in a 1-bit format. First portion of an analog finite impulse response filter 300 includes pre-selected number of delay elements 301 for receiving stream of data in the 1-bit format and outputting a plurality of signals in response. A switched capacitor digital-to-analog converter 106 forms a second portion of the finite impulse response filter 301 and has a plurality of elements each receiving one of the plurality of signals as selected to effectuate a set of filter coefficients, converter 106 summing the plurality of signals and outputting an analog data stream.
摘要翻译： 示出了数模转换电路100，其包括用于以1位格式处理数据的路径。 模拟有限脉冲响应滤波器300的第一部分包括用于接收1比特格式的数据流的预选数量的延迟元件301，并且响应地输出多个信号。 开关电容器数模转换器106形成有限脉冲响应滤波器301的第二部分，并且具有多个元件，每个元件接收所选择的多个信号中的一个以实现一组滤波器系数，转换器106将多个 的信号并输出模拟数据流。
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公开(公告)号：US20090292843A1
公开(公告)日：2009-11-26
申请号：US12154265
申请日：2008-05-21
申请人： Scott Haban , Dylan Hester , Ruifeng Sun
发明人： Scott Haban , Dylan Hester , Ruifeng Sun
CPC分类号： G06F13/4282
摘要： A demodulator can include first data and clock pads to couple the demodulator to a host device via a first bus, and second data and clock pads to couple the demodulator to a radio frequency (RF) tuner via a second bus. The device may further include passthrough logic to couple host data and a host clock from the first bus to the second bus and to couple tuner data from the second bus to the first bus during a passthrough mode. During this mode, however, the two buses may remain electrically decoupled. When the passthrough mode is disabled, the RF tuner is thus shielded from noise present on the first bus.
摘要翻译： 解调器可以包括经由第一总线将解调器耦合到主机设备的第一数据和时钟焊盘，以及经由第二总线将解调器耦合到射频（RF）调谐器的第二数据和时钟焊盘。 该设备还可以包括用于将主机数据和主机时钟从第一总线耦合到第二总线的通过逻辑，并且在直通模式期间将调谐器数据从第二总线耦合到第一总线。 然而，在这种模式下，两条总线可能保持电气分离。 当禁用直通模式时，RF调谐器被屏蔽，避免了存在于第一总线上的噪声。
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公开(公告)号：US20060068736A1
公开(公告)日：2006-03-30
申请号：US11112616
申请日：2005-04-22
申请人： Donald Kerth , James Maligeorgos , Dylan Hester , Lysander Lim , Augusto Marques , G. Tuttle
发明人： Donald Kerth , James Maligeorgos , Dylan Hester , Lysander Lim , Augusto Marques , G. Tuttle
CPC分类号： H03J7/04 , H03B5/36 , H03B2201/025 , H03J2200/10
摘要： A technique includes generating an analog voltage to control a frequency for an oscillator. The analog signal is converted into a digital signal, and the frequency is controlled in response to the digital signal.
摘要翻译： 一种技术包括产生模拟电压以控制振荡器的频率。 模拟信号被转换成数字信号，并且响应于数字信号来控制频率。
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公开(公告)号：US08151029B2
公开(公告)日：2012-04-03
申请号：US12981769
申请日：2010-12-30
申请人： Scott Haban , Dylan Hester , Ruifeng Sun
发明人： Scott Haban , Dylan Hester , Ruifeng Sun
IPC分类号： G06F13/00
CPC分类号： G06F13/4282
摘要： A demodulator can include first data and clock pads to couple the demodulator to a host device via a first bus, and second data and clock pads to couple the demodulator to a radio frequency (RF) tuner via a second bus. The device may further include passthrough logic to couple host data and a host clock from the first bus to the second bus and to couple tuner data from the second bus to the first bus during a passthrough mode. During this mode, however, the two buses may remain electrically decoupled. When the passthrough mode is disabled, the RF tuner is thus shielded from noise present on the first bus.
摘要翻译： 解调器可以包括经由第一总线将解调器耦合到主机设备的第一数据和时钟焊盘，以及经由第二总线将解调器耦合到射频（RF）调谐器的第二数据和时钟焊盘。 该设备还可以包括用于将主机数据和主机时钟从第一总线耦合到第二总线的通过逻辑，并且在直通模式期间将调谐器数据从第二总线耦合到第一总线。 然而，在这种模式下，两条总线可能保持电气分离。 当禁用直通模式时，RF调谐器被屏蔽，避免了第一个总线上存在的噪声。
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公开(公告)号：US20110099310A1
公开(公告)日：2011-04-28
申请号：US12981769
申请日：2010-12-30
申请人： Scott Haban , Dylan Hester , Ruifeng Sun
发明人： Scott Haban , Dylan Hester , Ruifeng Sun
CPC分类号： G06F13/4282
摘要： A demodulator can include first data and clock pads to couple the demodulator to a host device via a first bus, and second data and clock pads to couple the demodulator to a radio frequency (RF) tuner via a second bus. The device may further include passthrough logic to couple host data and a host clock from the first bus to the second bus and to couple tuner data from the second bus to the first bus during a passthrough mode. During this mode, however, the two buses may remain electrically decoupled. When the passthrough mode is disabled, the RF tuner is thus shielded from noise present on the first bus.
摘要翻译： 解调器可以包括经由第一总线将解调器耦合到主机设备的第一数据和时钟焊盘，以及经由第二总线将解调器耦合到射频（RF）调谐器的第二数据和时钟焊盘。 该设备还可以包括用于将主机数据和主机时钟从第一总线耦合到第二总线的通过逻辑，并且在直通模式期间将调谐器数据从第二总线耦合到第一总线。 然而，在这种模式下，两条总线可能保持电气分离。 当禁用直通模式时，RF调谐器被屏蔽，避免了第一个总线上存在的噪声。
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10.发明授权公开(公告)号：US06489901B1
公开(公告)日：2002-12-03
申请号：US09944738
申请日：2001-08-31
IPC分类号： H03M704
CPC分类号： H03H17/0294
摘要： A sample rate converter 210, 209 includes a filter 210 for processing digital data in response to a clock controlled by a clock enable signal, the filter 210 receiving the digital data at a first sampling rate and outputting digital data at a second sampling rate. Resampler circuitry 209 generates first selected periods of the clock enable signal having a first duty cycle approximating a ratio between the first sampling rate and the second sampling rate. Selectively, selected periods of the clock enable signal are generated having a second duty cycle for minimizing an error accumulated over the first selected periods of the clock enable signal.
摘要翻译： 采样率转换器210,209包括用于响应于由时钟使能信号控制的时钟来处理数字数据的滤波器210，滤波器210以第一采样率接收数字数据并以第二采样率输出数字数据。 重采样器电路209产生具有接近第一采样率和第二采样率之间的比率的第一占空比的时钟使能信号的第一选定周期。 选择性地，生成具有第二占空比的选择的时钟使能信号的周期，以最小化在时钟使能信号的第一选定周期上累积的误差。
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