公开(公告)号：US07563654B2

公开(公告)日：2009-07-21

申请号：US11647759

申请日：2006-12-29

申请人： Dong Sun Sheen ,  Seok Pyo Song ,  Sang Tae Ahn ,  Hyeon Ju An ,  Hyun Chul Sohn

发明人： Dong Sun Sheen ,  Seok Pyo Song ,  Sang Tae Ahn ,  Hyeon Ju An ,  Hyun Chul Sohn

IPC分类号： H01L21/335

CPC分类号： H01L27/0886 ,  H01L27/1214

摘要： A method for manufacturing a semiconductor device is disclosed. The method includes the steps of defining a trench into a field region of a semiconductor substrate having an active region and the field region; partially filing the trench with a flowable insulation layer; completely filling the trench with an isolation structure by depositing a close-packed insulation layer on the flowable insulation layer in the trench; etching through a portion of the close-packed insulation layer and etching into a partial thickness of the flowable insulation layer of the insulation structure to expose a portion of the active region; cleaning the resultant substrate having the active region relatively projected; forming spacers on etched portions of the flowable insulation layer where bowing occurs during the cleaning step; and forming gates on the active region and the insulation structure to border the exposed portion of the active region.

摘要翻译： 公开了一种制造半导体器件的方法。 该方法包括以下步骤：将沟槽定义为具有有源区域和场区域的半导体衬底的场区域; 用可流动的绝缘层部分地填充沟槽; 通过在沟槽中的可流动绝缘层上沉积紧密堆积的绝缘层，通过隔离结构完全填充沟槽; 蚀刻通过所述紧密封装绝缘层的一部分并蚀刻成所述绝缘结构的可流动绝缘层的部分厚度以暴露所述有源区的一部分; 清洁具有相对投影的活性区域的所得基材; 在清洁步骤中发生弯曲的可流动绝缘层的蚀刻部分上形成间隔物; 以及在所述有源区和所述绝缘结构上形成栅极以与所述有源区的所述暴露部分相接触。

公开(公告)号：US20070281454A1

公开(公告)日：2007-12-06

申请号：US11647759

申请日：2006-12-29

申请人： Dong Sun Sheen ,  Seok Pyo Song ,  Sang Tae Ahn ,  Hyeon Ju An ,  Hyun Chul Sohn

发明人： Dong Sun Sheen ,  Seok Pyo Song ,  Sang Tae Ahn ,  Hyeon Ju An ,  Hyun Chul Sohn

IPC分类号： H01L21/3205

CPC分类号： H01L27/0886 ,  H01L27/1214

摘要： A method for manufacturing a semiconductor device is disclosed. The method includes the steps of defining a trench into a field region of a semiconductor substrate having an active region and the field region; partially filing the trench with a flowable insulation layer; completely filling the trench with an isolation structure by depositing a close-packed insulation layer on the flowable insulation layer in the trench; etching through a portion of the close-packed insulation layer and etching into a partial thickness of the flowable insulation layer of the insulation structure to expose a portion of the active region; cleaning the resultant substrate having the active region relatively projected; forming spacers on etched portions of the flowable insulation layer where bowing occurs during the cleaning step; and forming gates on the active region and the insulation structure to border the exposed portion of the active region.

摘要翻译： 公开了一种制造半导体器件的方法。 该方法包括以下步骤：将沟槽定义为具有有源区域和场区域的半导体衬底的场区域; 用可流动的绝缘层部分地填充沟槽; 通过在沟槽中的可流动绝缘层上沉积紧密堆积的绝缘层，通过隔离结构完全填充沟槽; 蚀刻通过所述紧密封装绝缘层的一部分并蚀刻成所述绝缘结构的可流动绝缘层的部分厚度以暴露所述有源区的一部分; 清洁具有相对投影的活性区域的所得基材; 在清洁步骤中发生弯曲的可流动绝缘层的蚀刻部分上形成间隔物; 以及在所述有源区和所述绝缘结构上形成栅极以与所述有源区的所述暴露部分相接触。

公开(公告)号：US20070148840A1

公开(公告)日：2007-06-28

申请号：US11594579

申请日：2006-11-08

申请人： Dong Sun Sheen ,  Seok Pyo Song ,  Sang Tae Ahn ,  Hyun Chul Sohn

发明人： Dong Sun Sheen ,  Seok Pyo Song ,  Sang Tae Ahn ,  Hyun Chul Sohn

IPC分类号： H01L21/8234

CPC分类号： H01L21/823437 ,  H01L29/66795 ,  H01L29/7851

摘要： A fin transistor is formed by forming a hard mask layer on a substrate having an active region and a field region. The hard mask layer is etched to expose the field region. A trench is formed by etching the exposed field region. The trench is filled with an SOG layer. The hard mask layer is removed to expose the active region. An epi-silicon layer is formed on the exposed active region. The SOG layer is then partially etched from the upper end of the trench, thus filling a lower portion of the trench. A HDP oxide layer is deposited on the etched SOG layer filling the trench, thereby forming a field oxide layer composed of the SOG layer and the HDP oxide. The HDP oxide layer in the field oxide layer is etched to expose both side surfaces of the epi-silicon layer. A gate is then formed on the epi-silicon layer of which both side surfaces are exposed and the field oxide layer.

摘要翻译： 通过在具有有源区域和场区域的衬底上形成硬掩模层来形成鳍式晶体管。 蚀刻硬掩模层以暴露场区域。 通过蚀刻暴露的场区形成沟槽。 沟槽填充有SOG层。 去除硬掩模层以暴露活性区域。 在暴露的有源区上形成外延硅层。 然后从沟槽的上端部分地蚀刻SOG层，从而填充沟槽的下部。 HDP氧化物层沉积在填充沟槽的蚀刻SOG层上，从而形成由SOG层和HDP氧化物构成的场氧化物层。 蚀刻场氧化物层中的HDP氧化物层以露出外延硅层的两个侧表面。 然后在其两个侧表面暴露的外延硅层和场氧化物层上形成栅极。

公开(公告)号：US07655534B2

公开(公告)日：2010-02-02

申请号：US11594579

申请日：2006-11-08

申请人： Dong Sun Sheen ,  Seok Pyo Song ,  Sang Tae Ahn ,  Hyun Chul Sohn

发明人： Dong Sun Sheen ,  Seok Pyo Song ,  Sang Tae Ahn ,  Hyun Chul Sohn

IPC分类号： H01L21/762

CPC分类号： H01L21/823437 ,  H01L29/66795 ,  H01L29/7851

摘要： A fin transistor is formed by forming a hard mask layer on a substrate having an active region and a field region. The hard mask layer is etched to expose the field region. A trench is formed by etching the exposed field region. The trench is filled with an SOG layer. The hard mask layer is removed to expose the active region. An epi-silicon layer is formed on the exposed active region. The SOG layer is then partially etched from the upper end of the trench, thus filling a lower portion of the trench. A HDP oxide layer is deposited on the etched SOG layer filling the trench, thereby forming a field oxide layer composed of the SOG layer and the HDP oxide. The HDP oxide layer in the field oxide layer is etched to expose both side surfaces of the epi-silicon layer. A gate is then formed on the epi-silicon layer of which both side surfaces are exposed and the field oxide layer.

摘要翻译： 通过在具有有源区域和场区域的衬底上形成硬掩模层来形成鳍式晶体管。 蚀刻硬掩模层以暴露场区域。 通过蚀刻暴露的场区形成沟槽。 沟槽填充有SOG层。 去除硬掩模层以暴露活性区域。 在暴露的有源区上形成外延硅层。 然后从沟槽的上端部分地蚀刻SOG层，从而填充沟槽的下部。 HDP氧化物层沉积在填充沟槽的蚀刻SOG层上，从而形成由SOG层和HDP氧化物构成的场氧化物层。 蚀刻场氧化物层中的HDP氧化物层以露出外延硅层的两个侧表面。 然后在其两个侧表面暴露的外延硅层和场氧化物层上形成栅极。

公开(公告)号：US08178921B2

公开(公告)日：2012-05-15

申请号：US12638233

申请日：2009-12-15

申请人： Dong Sun Sheen ,  Sang Tae Ahn ,  Seok Pyo Song ,  Hyeon Ju An

发明人： Dong Sun Sheen ,  Sang Tae Ahn ,  Seok Pyo Song ,  Hyeon Ju An

IPC分类号： H01L29/78

CPC分类号： H01L29/78609 ,  H01L29/66795 ,  H01L29/7851

摘要： A semiconductor device includes a semiconductor substrate having an active region which includes a gate forming zone and an isolation region; an isolation layer formed in the isolation region of the semiconductor substrate to expose side surfaces of a portion of the active region including the gate forming zone, such that the portion of the active region including the gate forming zone constitutes a fin pattern; a silicon epitaxial layer formed on the active region including the fin pattern; and a gate formed to cover the fin pattern on which the silicon epitaxial layer is formed.

摘要翻译： 半导体器件包括具有包括栅极形成区和隔离区的有源区的半导体衬底; 隔离层，其形成在所述半导体衬底的隔离区域中，以暴露包括所述栅极形成区的有源区的一部分的侧表面，使得包括所述栅极形成区的有源区的所述部分构成鳍状图案; 形成在包括鳍状图案的有源区上的硅外延层; 以及形成为覆盖其上形成有硅外延层的鳍图案的栅极。

公开(公告)号：US07687371B2

公开(公告)日：2010-03-30

申请号：US12243133

申请日：2008-10-01

申请人： Dong Sun Sheen ,  Seok Pyo Song ,  Sang Tae Ahn ,  Hyeon Ju An

发明人： Dong Sun Sheen ,  Seok Pyo Song ,  Sang Tae Ahn ,  Hyeon Ju An

IPC分类号： H01L21/76

CPC分类号： H01L21/76224

摘要： An isolation structure of a semiconductor device is formed by forming a hard mask layer on a semiconductor substrate having active and field regions to expose the field region. A trench is defined by etching the exposed field region of the semiconductor substrate using the hard mask as an etch mask. An SOG layer is formed in the trench partially filling the trench. An amorphous aluminum oxide layer is formed on the resultant substrate including the SOG layer. An HDP layer is formed on the amorphous aluminum oxide layer to completely fill the trench. The HDP layer and the amorphous aluminum oxide layer are subjected to CMP to expose the hard mask. The hard mask and portions of the amorphous aluminum oxide layer that are formed on the HDP layer are removed. The amorphous aluminum oxide layer is crystallized.

摘要翻译： 半导体器件的隔离结构通过在具有活性和场区域的半导体衬底上形成硬掩模层以暴露场区而形成。 通过使用硬掩模作为蚀刻掩模蚀刻半导体衬底的曝光场区来限定沟槽。 SOG层形成在部分填充沟槽的沟槽中。 在包含SOG层的所得基板上形成无定形氧化铝层。 在无定形氧化铝层上形成HDP层以完全填充沟槽。 对HDP层和无定形氧化铝层进行CMP以暴露硬掩模。 去除形成在HDP层上的硬掩模和无定形氧化铝层的部分。 无定形氧化铝层结晶。

公开(公告)号：US07655533B2

公开(公告)日：2010-02-02

申请号：US11776885

申请日：2007-07-12

申请人： Dong Sun Sheen ,  Sang Tae Ahn ,  Seok Pyo Song ,  Hyeon Ju An

发明人： Dong Sun Sheen ,  Sang Tae Ahn ,  Seok Pyo Song ,  Hyeon Ju An

IPC分类号： H01L21/762

CPC分类号： H01L29/78609 ,  H01L29/66795 ,  H01L29/7851

摘要： A semiconductor device includes a semiconductor substrate having an active region which includes a gate forming zone and an isolation region; an isolation layer formed in the isolation region of the semiconductor substrate to expose side surfaces of a portion of the active region including the gate forming zone, such that the portion of the active region including the gate forming zone constitutes a fin pattern; a silicon epitaxial layer formed on the active region including the fin pattern; and a gate formed to cover the fin pattern on which the silicon epitaxial layer is formed.

摘要翻译： 半导体器件包括具有包括栅极形成区和隔离区的有源区的半导体衬底; 隔离层，其形成在所述半导体衬底的隔离区域中，以暴露包括所述栅极形成区的有源区的一部分的侧表面，使得包括所述栅极形成区的有源区的所述部分构成鳍状图案; 形成在包括鳍状图案的有源区上的硅外延层; 以及形成为覆盖其上形成有硅外延层的鳍图案的栅极。

公开(公告)号：US07501687B2

公开(公告)日：2009-03-10

申请号：US11647764

申请日：2006-12-29

申请人： Dong Sun Sheen ,  Seok Pyo Song ,  Sang Tae Ahn ,  Hyeon Ju An

发明人： Dong Sun Sheen ,  Seok Pyo Song ,  Sang Tae Ahn ,  Hyeon Ju An

IPC分类号： H01L27/088

CPC分类号： H01L21/76224

摘要： An isolation structure of a semiconductor device is formed by forming a hard mask layer on a semiconductor substrate having active and field regions to expose the field region. A trench is defined by etching the exposed field region of the semiconductor substrate using the hard mask as an etch mask. An SOG layer is formed in the trench partially filling the trench. An amorphous aluminum oxide layer is formed on the resultant substrate including the SOG layer. An HDP layer is formed on the amorphous aluminum oxide layer to completely fill the trench. The HDP layer and the amorphous aluminum oxide layer are subjected to CMP to expose the hard mask. The hard mask and portions of the amorphous aluminum oxide layer that are formed on the HDP layer are removed. The amorphous aluminum oxide layer is crystallized.

摘要翻译： 半导体器件的隔离结构通过在具有活性和场区域的半导体衬底上形成硬掩模层以暴露场区而形成。 通过使用硬掩模作为蚀刻掩模蚀刻半导体衬底的曝光场区来限定沟槽。 SOG层形成在部分填充沟槽的沟槽中。 在包含SOG层的所得基板上形成无定形氧化铝层。 在无定形氧化铝层上形成HDP层以完全填充沟槽。 对HDP层和无定形氧化铝层进行CMP以暴露硬掩模。 去除形成在HDP层上的硬掩模和无定形氧化铝层的部分。 无定形氧化铝层结晶。

公开(公告)号：US20080001249A1

公开(公告)日：2008-01-03

申请号：US11647764

申请日：2006-12-29

申请人： Dong Sun Sheen ,  Seok Pyo Song ,  Sang Tae Ahn ,  Hyeon Ju An

发明人： Dong Sun Sheen ,  Seok Pyo Song ,  Sang Tae Ahn ,  Hyeon Ju An

IPC分类号： H01L29/00

CPC分类号： H01L21/76224

摘要： An isolation structure of a semiconductor device is formed by forming a hard mask layer on a semiconductor substrate having active and field regions to expose the field region. A trench is defined by etching the exposed field region of the semiconductor substrate using the hard mask as an etch mask. An SOG layer is formed in the trench partially filling the trench. An amorphous aluminum oxide layer is formed on the resultant substrate including the SOG layer. An HDP layer is formed on the amorphous aluminum oxide layer to completely fill the trench. The HDP layer and the amorphous aluminum oxide layer are subjected to CMP to expose the hard mask. The hard mask and portions of the amorphous aluminum oxide layer that are formed on the HDP layer are removed. The amorphous aluminum oxide layer is crystallized.

摘要翻译： 半导体器件的隔离结构通过在具有活性和场区域的半导体衬底上形成硬掩模层以暴露场区而形成。 通过使用硬掩模作为蚀刻掩模蚀刻半导体衬底的曝光场区来限定沟槽。 SOG层形成在部分填充沟槽的沟槽中。 在包含SOG层的所得基板上形成无定形氧化铝层。 在无定形氧化铝层上形成HDP层以完全填充沟槽。 对HDP层和无定形氧化铝层进行CMP以暴露硬掩模。 去除形成在HDP层上的硬掩模和无定形氧化铝层的部分。 无定形氧化铝层结晶。

公开(公告)号：US06949447B2

公开(公告)日：2005-09-27

申请号：US10738399

申请日：2003-12-17

申请人： Sang Tae Ahn ,  Sung Woong Chung ,  Hyun Chul Sohn

发明人： Sang Tae Ahn ,  Sung Woong Chung ,  Hyun Chul Sohn

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76224

摘要： A method for fabricating an isolation layer in a semiconductor device is disclosed. The disclosed method comprises steps of: forming a trench on a semiconductor substrate; forming a flowing insulating layer within the trench; making the insulating layer precise; and forming a precise insulating layer over an upper surface of the whole structure on which the flowing insulating layer is formed. According to the method of fabricating an isolation layer in a semiconductor device, occurrence of fine pores at adjacent active regions of sidewalls in a trench can be prevented.

摘要翻译： 公开了一种在半导体器件中制造隔离层的方法。 所公开的方法包括以下步骤：在半导体衬底上形成沟槽; 在沟槽内形成流动的绝缘层; 使绝缘层精确; 并在其上形成有流动绝缘层的整个结构的上表面上形成精确的绝缘层。 根据在半导体器件中制造隔离层的方法，可以防止在沟槽中的侧壁的相邻有源区产生细孔。