Clock driver
    1.
    发明授权
    Clock driver 有权
    时钟驱动

    公开(公告)号:US07521978B2

    公开(公告)日:2009-04-21

    申请号:US11479290

    申请日:2006-06-29

    IPC分类号: G06F1/04

    CPC分类号: G06F1/10

    摘要: A clock driver is provided. A first driving unit is configured with a plurality of drivers and receives a first clock signal to drive a first pumping clock. A second driving unit is configured with a plurality of drivers and receives a second clock signal to drive a second pumping clock. A charge recycling switch is connected between an output terminal of the first driving unit and an output terminal of the second driving unit. A switch controller selectively transfers an input clock signal of the first or second driving unit to the charge recycling switch in response to the first and second pumping clock signals.

    摘要翻译: 提供时钟驱动程序。 第一驱动单元配置有多个驱动器并且接收第一时钟信号以驱动第一泵送时钟。 第二驱动单元配置有多个驱动器并且接收第二时钟信号以驱动第二抽时钟。 电荷循环开关连接在第一驱动单元的输出端和第二驱动单元的输出端之间。 开关控制器响应于第一和第二抽吸时钟信号选择性地将第一或第二驱动单元的输入时钟信号传送到电荷再循环开关。

    Clock driver
    2.
    发明申请
    Clock driver 有权
    时钟驱动

    公开(公告)号:US20070103220A1

    公开(公告)日:2007-05-10

    申请号:US11479290

    申请日:2006-06-29

    IPC分类号: G06F1/04

    CPC分类号: G06F1/10

    摘要: A clock driver is provided. A first driving unit is configured with a plurality of drivers and receives a first clock signal to drive a first pumping clock. A second driving unit is configured with a plurality of drivers and receives a second clock signal to drive a second pumping clock. A charge recycling switch is connected between an output terminal of the first driving unit and an output terminal of the second driving unit. A switch controller selectively transfers an input clock signal of the first or second driving unit to the charge recycling switch in response to the first and second pumping clock signals.

    摘要翻译: 提供时钟驱动程序。 第一驱动单元配置有多个驱动器并且接收第一时钟信号以驱动第一泵送时钟。 第二驱动单元配置有多个驱动器并且接收第二时钟信号以驱动第二抽时钟。 电荷循环开关连接在第一驱动单元的输出端和第二驱动单元的输出端之间。 开关控制器响应于第一和第二抽吸时钟信号选择性地将第一或第二驱动单元的输入时钟信号传送到电荷再循环开关。

    Analog-digital converter and on-die thermal sensor including the same
    3.
    发明授权
    Analog-digital converter and on-die thermal sensor including the same 有权
    模拟数字转换器和片上热传感器包括相同的

    公开(公告)号:US07880661B2

    公开(公告)日:2011-02-01

    申请号:US11819816

    申请日:2007-06-29

    IPC分类号: H03M1/50

    CPC分类号: H03M1/56 G01K7/01 G01K2219/00

    摘要: An on-die thermal sensor includes an integrating analog-digital converter not requiring a negative reference voltage input. The on die thermal sensor includes a band gap unit, an integrating unit and a counting unit. The band gap unit senses a temperature to output a first voltage corresponding to the sensed temperature. The integrating unit integrates a difference between a reference voltage and a comparing voltage to output a second voltage wherein the comparing voltage has a voltage level higher than that of the reference voltage. The counting unit counts clocks of a clock signal input thereto until the second voltage reaches the first voltage, thereby outputting a thermal code corresponding to the voltage level of the first voltage.

    摘要翻译: 片上热传感器包括不需要负参考电压输入的积分模数转换器。 管芯热传感器包括带隙单元,积分单元和计数单元。 带隙单元感测温度以输出对应于感测温度的第一电压。 积分单元将参考电压和比较电压之间的差分相加以输出第二电压,其中比较电压的电压电平高于参考电压的电压电平。 计数单元对输入的时钟信号的时钟进行计数,直到第二电压达到第一电压,从而输出与第一电压的电压电平对应的热代码。

    Analog-digital converter and on-die thermal sensor including the same
    4.
    发明申请
    Analog-digital converter and on-die thermal sensor including the same 有权
    模拟数字转换器和片上热传感器包括相同的

    公开(公告)号:US20080180300A1

    公开(公告)日:2008-07-31

    申请号:US11819816

    申请日:2007-06-29

    IPC分类号: H03M1/34 G06F1/20 H03M1/50

    CPC分类号: H03M1/56 G01K7/01 G01K2219/00

    摘要: An on-die thermal sensor includes an integrating analog-digital converter not requiring a negative reference voltage input. The on die thermal sensor includes a band gap unit, an integrating unit and a counting unit. The band gap unit senses a temperature to output a first voltage corresponding to the sensed temperature. The integrating unit integrates a difference between a reference voltage and a comparing voltage to output a second voltage wherein the comparing voltage has a voltage level higher than that of the reference voltage. The counting unit counts clocks of a clock signal input thereto until the second voltage reaches the first voltage, thereby outputting a thermal code corresponding to the voltage level of the first voltage.

    摘要翻译: 片上热传感器包括不需要负参考电压输入的积分模数转换器。 管芯热传感器包括带隙单元,积分单元和计数单元。 带隙单元感测温度以输出对应于感测温度的第一电压。 积分单元将参考电压和比较电压之间的差分相加以输出第二电压,其中比较电压的电压电平高于参考电压的电压电平。 计数单元对输入的时钟信号的时钟进行计数,直到第二电压达到第一电压,从而输出与第一电压的电压电平对应的热代码。

    SAFETY MANAGEMENT SYSTEM FOR MANDATORY JOB SAFETY ANALYSIS AND METHOD THEREOF
    5.
    发明申请
    SAFETY MANAGEMENT SYSTEM FOR MANDATORY JOB SAFETY ANALYSIS AND METHOD THEREOF 审中-公开
    安全管理体系的强制性作业安全性分析及其方法

    公开(公告)号:US20130191300A1

    公开(公告)日:2013-07-25

    申请号:US13643545

    申请日:2011-12-07

    IPC分类号: G06Q50/26 G06Q10/00

    摘要: The present invention relates to a safety management system including a JSA draw-up module configured to display a screen for drawing up a job safety analysis worksheet for job safety analysis (JSA) and to draw up the job safety analysis worksheet on the basis of the information inputted by a user; a storage module configured to store the job safety analysis worksheet drawn up by the JSA draw-up module into a database (DB) and to store task hazard information drawn up for each unit task that can be referred for the job safety analysis worksheet into a database; and a inventory module configured to manage the job safety analysis worksheet and the task hazard information stored in the storage module and to create a new job safety analysis worksheet and new task hazard information in accordance with a request from the JSA draw-up module, and a method thereof.

    摘要翻译: 本发明涉及一种安全管理系统,包括JSA绘图模块,其被配置为显示用于绘制作业安全性分析工作安全分析工作表(JSA)的画面,并且基于该工作安全分析工作表 由用户输入的信息; 存储模块,其被配置为将由JSA绘图模块制定的作业安全分析工作表存储到数据库(DB)中,并将为工作安全分析工作表引用的每个单元任务绘制的任务危险信息存储为 数据库; 以及库存模块,被配置为管理存储在存储模块中的作业安全分析工作表和任务危险信息,并且根据JSA制图模块的请求创建新的作业安全分析工作表和新的任务危险信息,以及 其方法。

    APPARATUS FOR DECODING RESIDUAL DATA BASED ON BIT PLANE AND METHOD THEREOF
    6.
    发明申请
    APPARATUS FOR DECODING RESIDUAL DATA BASED ON BIT PLANE AND METHOD THEREOF 失效
    用于根据位平面解码残留数据的装置及其方法

    公开(公告)号:US20120128075A1

    公开(公告)日:2012-05-24

    申请号:US13226765

    申请日:2011-09-07

    IPC分类号: H04N7/26

    摘要: An apparatus for decoding residual data based on a bit plane and a method thereof, capable of achieving a significant reduction in data traffic between a memory and a functional module in a parallel decoding system, include a variable length decoding module configured to generate residual data for each macroblock from a bit stream, divide the residual data into groups, and generate a bit plane regarding each of the groups, and a variable length decoding memory configured to store the bit plane generated from the variable length decoding module and store the residual data of the groups according to a value of the bit plane.

    摘要翻译: 一种用于解码基于位平面的残差数据的装置及其方法,其能够实现并行解码系统中的存储器与功能模块之间的数据流量的显着降低,包括:可变长度解码模块,被配置为产生残留数据, 来自位流的每个宏块将残差数据分成组,并且生成关于每个组的位平面;以及可变长度解码存储器,被配置为存储从可变长度解码模块生成的位平面,并存储 该组根据位平面的值。

    Multi-port semiconductor memory device
    7.
    发明授权
    Multi-port semiconductor memory device 有权
    多端口半导体存储器件

    公开(公告)号:US07586801B2

    公开(公告)日:2009-09-08

    申请号:US12072548

    申请日:2008-02-26

    IPC分类号: G11C11/00

    CPC分类号: G11C29/26 G11C8/16

    摘要: A semiconductor memory device includes: a plurality of ports configured to perform a serial input/output (I/O) data communication with external devices; a plurality of banks configured to perform a parallel I/O data communication with the ports; a global data bus configured to transmit a signal between the banks and the ports; a test mode determiner configured to determine an operation mode of the semiconductor memory device by generating a test mode enable signal in response to a test mode control signal; a test I/O controller configured to transmit and receive a test signal with the ports in response to the test mode enable signal during a port test mode; and a plurality of selectors, each of which is configured to receive the test signal output from the corresponding port in series and feedback the test signal to the corresponding port.

    摘要翻译: 半导体存储器件包括:多个端口,被配置为执行与外部设备的串行输入/输出(I / O)数据通信; 配置为执行与所述端口的并行I / O数据通信的多个存储体; 全局数据总线,被配置为在所述存储体和所述端口之间传输信号; 测试模式确定器,被配置为通过响应于测试模式控制信号产生测试模式使能信号来确定半导体存储器件的操作模式; 测试I / O控制器,被配置为在端口测试模式期间响应于测试模式使能信号在端口上发送和接收测试信号; 以及多个选择器,每个选择器被配置为从串行的相应端口接收输出的测试信号,并将测试信号反馈到相应的端口。

    On die thermal sensor having analog-to-digital converter for use in semiconductor memory device
    8.
    发明申请
    On die thermal sensor having analog-to-digital converter for use in semiconductor memory device 有权
    具有用于半导体存储器件的模拟 - 数字转换器的管芯式热传感器

    公开(公告)号:US20080106451A1

    公开(公告)日:2008-05-08

    申请号:US11819795

    申请日:2007-06-29

    IPC分类号: H03M1/12 G01K1/00

    摘要: An On Die Thermal Sensor (ODTS) of a semiconductor memory device includes: a temperature detector for detecting an internal temperature of the semiconductor memory device to generate a temperature voltage corresponding to the detected internal temperature; a tracking ADC for outputting a digital code by comparing the temperature voltage with a tracking voltage and performing a counting operation to the result of comparison; and an operation controller for controlling operations of the temperature detector and the analog-to-digital converter, wherein the tracking ADC performs the counting operation using a first tracking scheme having a relatively large unit variation width of the digital code value during an initial tracking period and a second tracking scheme having a relatively small unit variation width of the digital code value after the initial tracking period.

    摘要翻译: 半导体存储器件的散热片传感器(ODTS)包括:温度检测器,用于检测半导体存储器件的内部温度以产生对应于检测到的内部温度的温度电压; 跟踪ADC,用于通过将温度电压与跟踪电压进行比较来输出数字代码,并对比较结果执行计数操作; 以及用于控制温度检测器和模数转换器的操作的操作控制器,其中跟踪ADC使用在初始跟踪周期期间具有数字码值的相对大的单位变化宽度的第一跟踪方案来执行计数操作 以及在初始跟踪周期之后具有数字码值的相对小的单位变化宽度的第二跟踪方案。

    Delay locked loop circuit
    9.
    发明申请
    Delay locked loop circuit 有权
    延时锁定回路电路

    公开(公告)号:US20070069778A1

    公开(公告)日:2007-03-29

    申请号:US11478094

    申请日:2006-06-30

    申请人: Hoon Choi Jae-Jin Lee

    发明人: Hoon Choi Jae-Jin Lee

    IPC分类号: H03L7/06

    摘要: A DLL of a memory device having a normal mode and a power down mode includes a clock buffer for buffering an external clock signal to output an internal clock signal. A power down mode controller generates a power down mode control signal to define the normal mode or the power down mode in response to a clock enable signal. A source clock generation unit receives the internal clock signal to generate a DLL source clock signal under the control of the power down mode control signal. A phase update unit performs a phase update operation based on the DLL source clock signal to output a DLL clock signal.

    摘要翻译: 具有正常模式和掉电模式的存储器件的DLL包括用于缓冲外部时钟信号以输出内部时钟信号的时钟缓冲器。 断电模式控制器响应于时钟使能信号产生掉电模式控制信号以定义正常模式或掉电模式。 源时钟生成单元在停电模式控制信号的控制下接收内部时钟信号以产生DLL源时钟信号。 相位更新单元基于DLL源时钟信号执行相位更新操作,以输出DLL时钟信号。

    Multi-port memory device
    10.
    发明申请
    Multi-port memory device 有权
    多端口存储设备

    公开(公告)号:US20060238215A1

    公开(公告)日:2006-10-26

    申请号:US11322789

    申请日:2005-12-29

    IPC分类号: H03K19/195 G11C19/08

    CPC分类号: G11C7/1075

    摘要: A multi-port memory device improves efficiency of a global data drive by controlling the global data bus to transmit data in a predetermined range. The multi-port memory device includes a global data bus; transmitters and receivers; a termination unit for controlling the global data bus to transmit the data in a range between a first voltage and a second voltage in response to an active mode signal; and a voltage generator for generating the first and the second voltages. The first voltage is higher than a ground voltage and the second voltage is lower than a power supply voltage.

    摘要翻译: 多端口存储器件通过控制全局数据总线在预定范围内传输数据来提高全局数据驱动的效率。 多端口存储器件包括全局数据总线; 发射机和接收机; 终端单元,用于响应于活动模式信号,控制全局数据总线在第一电压和第二电压之间的范围内传输数据; 以及用于产生第一和第二电压的电压发生器。 第一电压高于接地电压,第二电压低于电源电压。