公开(公告)号：US20100240323A1

公开(公告)日：2010-09-23

申请号：US12407700

申请日：2009-03-19

Applicant: Dongjiang Qiao ,  Frederic Bossu

Inventor： Dongjiang Qiao ,  Frederic Bossu

IPC: H04B1/40 ,  H03B19/00

CPC classification number: G06F1/06 ,  H03K23/667 ,  H03K23/68

Abstract: A synchronized frequency divider that can divide a clock signal in frequency and provide differential output signals having good signal characteristics is described. In one exemplary design, the synchronized frequency divider includes a single-ended frequency divider and a synchronization circuit. The single-ended frequency divider divides the clock signal in frequency and provides first and second single-ended signals, which may be complementary signals having timing skew. The synchronization circuit resamples the first and second single-ended signals based on the clock signal and provides differential output signals having reduced timing skew. In one exemplary design, the synchronization circuit includes first and second switches and first and second inverters. The first switch and the first inverter form a first sample-and-hold circuit or a first latch that resamples the first single-ended signal. The second switch and the second inverter form a second sample-and-hold circuit or a second latch that resamples the second single-ended signal.

Abstract translation: 描述了可以将时钟信号分频并提供具有良好信号特性的差分输出信号的同步分频器。 在一个示例性设计中，同步分频器包括单端分频器和同步电路。 单端分频器分频时钟信号，并提供第一和第二单端信号，这可能是具有定时偏移的互补信号。 同步电路基于时钟信号重新采样第一和第二单端信号，并提供具有减小的定时偏差的差分输出信号。 在一个示例性设计中，同步电路包括第一和第二开关以及第一和第二逆变器。 第一开关和第一反相器形成第一采样保持电路或重新采样第一单端信号的第一锁存器。 第二开关和第二反相器形成第二采样保持电路或重新采样第二单端信号的第二锁存器。

公开(公告)号：US08791740B2

公开(公告)日：2014-07-29

申请号：US12724337

申请日：2010-03-15

Applicant: Dongjiang Qiao ,  Bhushan S. Asuri ,  Junxiong Deng ,  Frederic Bossu

Inventor： Dongjiang Qiao ,  Bhushan S. Asuri ,  Junxiong Deng ,  Frederic Bossu

IPC: H03K3/289

CPC classification number: H04B1/408 ,  H03B19/00 ,  H03L7/0812 ,  H04B1/109

Abstract: A method for reducing average current consumption in a local oscillator (LO) path is disclosed. An LO signal is received at a master frequency divider and a slave frequency divider. Output from the master frequency divider is mixed with an input signal to produce a first mixed output. Output from the slave frequency divider is mixed with the input signal to produce a second mixed output. The second mixed output is forced to be in phase with the first mixed output.

Abstract translation: 公开了一种用于降低本地振荡器（LO）路径中的平均电流消耗的方法。 在主分频器和从分频器处接收LO信号。 主分频器的输出与输入信号混合，产生第一个混合输出。 来自从分频器的输出与输入信号混合，产生第二个混合输出。 第二个混合输出被强制与第一个混合输出同相。

公开(公告)号：US07825703B2

公开(公告)日：2010-11-02

申请号：US12193693

申请日：2008-08-18

Applicant: Dongjiang Qiao ,  Frederic Bossu

Inventor： Dongjiang Qiao ,  Frederic Bossu

IPC: H03B19/00

CPC classification number: H03L7/183 ,  H03H11/265 ,  H03K23/42 ,  H03L7/0812

Abstract: A local oscillator includes a programmable frequency divider coupled to the output of a VCO. The frequency divider can be set to frequency divide by three. Regardless of the divisor, the frequency divider outputs quadrature signals (I, Q) that differ from each other in phase by ninety degrees. To divide by three, the frequency divider includes a divide-by-three frequency divider. The divide-by-three frequency divider includes a divide-by-three circuit, a delay circuit, and a feedback circuit. The divide-by-three circuit frequency divides a signal from the VCO and generates therefrom three signals C, A′ and B that differ from each other in phase by one hundred twenty degrees. The delay circuit delays signal A′ to generate a delayed version A of the signal A′. The feedback circuit controls the delay circuit such that the delayed version A (I) is ninety degrees out of phase with respect to the signal C (Q).

Abstract translation: 本地振荡器包括耦合到VCO的输出的可编程分频器。 分频器可以设置为三分频。 除了除数以外，分频器输出相位相差九十度的正交信号（I，Q）。 为了除以3，分频器包括一个除以三分频器。 除以三分频器包括三分之一电路，延迟电路和反馈电路。 三分频电路分频来自VCO的信号，从而产生三相彼此相差一百二十度的信号C，A'和B。 延迟电路延迟信号A'以产生信号A'的延迟版本A. 反馈电路控制延迟电路，使得延迟版本A（I）相对于信号C（Q）相差90度。

公开(公告)号：US08344765B2

公开(公告)日：2013-01-01

申请号：US12836454

申请日：2010-07-14

Applicant: Dongjiang Qiao ,  Frederic Bossu

Inventor： Dongjiang Qiao ,  Frederic Bossu

IPC: H03B19/06 ,  H03K21/00

CPC classification number: H03K23/40 ,  H03K21/00

Abstract: A method for dividing the frequency of a signal using a configurable dividing ratio is disclosed. An input signal with a first frequency is received at clocked switches in a frequency divider with a configurable dividing ratio. Non-clocked switches inside the frequency divider are operated to select one of multiple dividing ratios. An output signal is output with a second frequency that is the first frequency divided by the selected dividing ratio.

Abstract translation: 公开了一种使用可配置分频比对信号频率进行分频的方法。 具有第一频率的输入信号在具有可配置分频比的分频器中的时钟开关处被接收。 操作分频器内的非时钟开关可以选择多个分频比之一。 输出信号以第一频率除以选择的分频比的第二频率输出。

公开(公告)号：US08265568B2

公开(公告)日：2012-09-11

申请号：US12407700

申请日：2009-03-19

Applicant: Dongjiang Qiao ,  Frederic Bossu

Inventor： Dongjiang Qiao ,  Frederic Bossu

IPC: H03K25/00

CPC classification number: G06F1/06 ,  H03K23/667 ,  H03K23/68

Abstract: A synchronized frequency divider that can divide a clock signal in frequency and provide differential output signals having good signal characteristics is described. In one exemplary design, the synchronized frequency divider includes a single-ended frequency divider and a synchronization circuit. The single-ended frequency divider divides the clock signal in frequency and provides first and second single-ended signals, which may be complementary signals having timing skew. The synchronization circuit resamples the first and second single-ended signals based on the clock signal and provides differential output signals having reduced timing skew. In one exemplary design, the synchronization circuit includes first and second switches and first and second inverters. The first switch and the first inverter form a first sample-and-hold circuit or a first latch that resamples the first single-ended signal. The second switch and the second inverter form a second sample-and-hold circuit or a second latch that resamples the second single-ended signal.

Abstract translation: 描述了可以将时钟信号分频并提供具有良好信号特性的差分输出信号的同步分频器。 在一个示例性设计中，同步分频器包括单端分频器和同步电路。 单端分频器分频时钟信号，并提供第一和第二单端信号，这可能是具有定时偏移的互补信号。 同步电路基于时钟信号重新采样第一和第二单端信号，并提供具有减小的定时偏差的差分输出信号。 在一个示例性设计中，同步电路包括第一和第二开关以及第一和第二逆变器。 第一开关和第一反相器形成第一采样保持电路或重新采样第一单端信号的第一锁存器。 第二开关和第二反相器形成第二采样保持电路或重新采样第二单端信号的第二锁存器。

公开(公告)号：US20110012647A1

公开(公告)日：2011-01-20

申请号：US12836454

申请日：2010-07-14

Applicant: Dongjiang Qiao ,  Frederic Bossu

Inventor： Dongjiang Qiao ,  Frederic Bossu

IPC: H03B19/00

CPC classification number: H03K23/40 ,  H03K21/00

Abstract: A method for dividing the frequency of a signal using a configurable dividing ratio is disclosed. An input signal with a first frequency is received at clocked switches in a frequency divider with a configurable dividing ratio. Non-clocked switches inside the frequency divider are operated to select one of multiple dividing ratios. An output signal is output with a second frequency that is the first frequency divided by the selected dividing ratio.

Abstract translation: 公开了一种使用可配置分频比对信号频率进行分频的方法。 具有第一频率的输入信号在具有可配置分频比的分频器中的时钟开关处被接收。 操作分频器内的非时钟开关可以选择多个分频比之一。 输出信号以第一频率除以选择的分频比的第二频率输出。

公开(公告)号：US20110012648A1

公开(公告)日：2011-01-20

申请号：US12724337

申请日：2010-03-15

Applicant: Dongjiang Qiao ,  Bhushan S. Asuri ,  Junxiong Deng ,  Frederic Bossu

Inventor： Dongjiang Qiao ,  Bhushan S. Asuri ,  Junxiong Deng ,  Frederic Bossu

IPC: H03L7/00

CPC classification number: H04B1/408 ,  H03B19/00 ,  H03L7/0812 ,  H04B1/109

Abstract: A method for reducing average current consumption in a local oscillator (LO) path is disclosed. An LO signal is received at a master frequency divider and a slave frequency divider. Output from the master frequency divider is mixed with an input signal to produce a first mixed output. Output from the slave frequency divider is mixed with the input signal to produce a second mixed output. The second mixed output is forced to be in phase with the first mixed output.

Abstract translation: 公开了一种用于降低本地振荡器（LO）路径中的平均电流消耗的方法。 在主分频器和从分频器处接收LO信号。 主分频器的输出与输入信号混合，产生第一个混合输出。 来自从分频器的输出与输入信号混合，产生第二个混合输出。 第二个混合输出被强制与第一个混合输出同相。

公开(公告)号：US20100039153A1

公开(公告)日：2010-02-18

申请号：US12193693

申请日：2008-08-18

Applicant: Dongjiang Qiao ,  Frederic Bossu

Inventor： Dongjiang Qiao ,  Frederic Bossu

IPC: H03H11/16

CPC classification number: H03L7/183 ,  H03H11/265 ,  H03K23/42 ,  H03L7/0812

Abstract: A local oscillator includes a programmable frequency divider coupled to the output of a VCO. The frequency divider can be set to frequency divide by three. Regardless of the divisor, the frequency divider outputs quadrature signals (I, Q) that differ from each other in phase by ninety degrees. To divide by three, the frequency divider includes a divide-by-three frequency divider. The divide-by-three frequency divider includes a divide-by-three circuit, a delay circuit, and a feedback circuit. The divide-by-three circuit frequency divides a signal from the VCO and generates therefrom three signals C, A′ and B that differ from each other in phase by one hundred twenty degrees. The delay circuit delays signal A′ to generate a delayed version A of the signal A′. The feedback circuit controls the delay circuit such that the delayed version A (I) is ninety degrees out of phase with respect to the signal C (Q).

Abstract translation: 本地振荡器包括耦合到VCO的输出的可编程分频器。 分频器可以设置为三分频。 除了除数以外，分频器输出相位相差九十度的正交信号（I，Q）。 为了除以3，分频器包括一个除以三分频器。 除以三分频器包括三分之一电路，延迟电路和反馈电路。 三分频电路分频来自VCO的信号，从而产生三相彼此相差一百二十度的信号C，A'和B。 延迟电路延迟信号A'以产生信号A'的延迟版本A. 反馈电路控制延迟电路，使得延迟版本A（I）相对于信号C（Q）相差90度。

公开(公告)号：US08639205B2

公开(公告)日：2014-01-28

申请号：US12052657

申请日：2008-03-20

Applicant: Junxiong Deng ,  Aristotele Hadjichristos ,  Aleksandar Tasic ,  Frederic Bossu

Inventor： Junxiong Deng ,  Aristotele Hadjichristos ,  Aleksandar Tasic ,  Frederic Bossu

IPC: H04B1/26

CPC classification number: H04W52/0206 ,  H03G3/20 ,  H04B1/16

Abstract: An exemplary embodiment disclosed comprises a mixer having a plurality of input leads; a first degenerative impedance element coupled to a first input lead of the mixer; a second degenerative impedance element coupled to a second input lead of the mixer; and a local oscillator (LO) system comprising a plurality of duty cycle modes to generate a LO signal for the mixer, the local oscillator system operates in a first duty cycle based on a first gain state of the mixer, and in a second duty cycle based on a second gain state of the mixer.

Abstract translation: 公开的示例性实施例包括具有多个输入引线的混合器; 耦合到混合器的第一输入引线的第一退化阻抗元件; 耦合到混合器的第二输入引线的第二退化阻抗元件; 以及本地振荡器（LO）系统，其包括多个占空比模式以产生混频器的LO信号，本地振荡器系统基于混频器的第一增益状态在第一占空比中工作，并且在第二占空比 基于混频器的第二增益状态。

公开(公告)号：US08615205B2

公开(公告)日：2013-12-24

申请号：US12259178

申请日：2008-10-27

Applicant: Ojas M. Choksi ,  Frederic Bossu

Inventor： Ojas M. Choksi ,  Frederic Bossu

IPC: H03C1/62

CPC classification number: H04L5/1461 ,  H03D3/009 ,  H03M1/1019 ,  H03M1/66 ,  H04L27/0014 ,  H04L2027/0016 ,  H04L2027/0018 ,  H04L2027/0024

Abstract: Techniques are provided for reducing mismatch between the in-phase (I) and quadrature (Q) channels of a communications transmitter or receiver. In an exemplary embodiment, separate voltages are applied to bias the gates or bulks of the transistors in a mixer of the I channel versus a mixer of the Q channel. In another exemplary embodiment, separate voltages are applied to bias the common-mode reference voltage of a transimpedance amplifier associated with each channel. Techniques are further provided for deriving bias voltages to minimize a measured residual sideband in a received or transmitted signal, or to optimize other parameters of the received or transmitted signal. Techniques for generating separate bias voltages using a bidirectional and unidirectional current digital-to-analog converter (DAC) are also disclosed.

Abstract translation: 提供了用于减少通信发射机或接收机的同相（I）和正交（Q）信道之间的失配的技术。 在示例性实施例中，施加单独的电压以在I通道的混频器中与Q通道的混频器偏置晶体管的栅极或体积。 在另一个示例性实施例中，施加单独的电压以偏置与每个通道相关联的跨阻抗放大器的共模参考电压。 还提供了用于导出偏置电压以最小化接收或发射信号中测量的残留边带或者优化接收或发射信号的其它参数的技术。 还公开了使用双向和单向电流数模转换器（DAC）产生单独偏置电压的技术。