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    RESISTOR TUNING
    1.
    发明申请
    RESISTOR TUNING 有权
    电阻调谐

    公开(公告)号：US20050230785A1

    公开(公告)日：2005-10-20

    申请号：US10709115

    申请日：2004-04-14

    申请人： Douglas Coolbaugh ,  Ebenezer Eshun ,  Robert Rassel ,  Anthony Stamper

    发明人： Douglas Coolbaugh ,  Ebenezer Eshun ,  Robert Rassel ,  Anthony Stamper

    IPC分类号： H01C17/26 ,  H01L29/76

    CPC分类号： H01C17/267

    摘要： A structure for resistors and the method for tuning the same. The resistor comprises an electrically conducting region coupled to a liner region. Both the electrically conducting region and the liner region are electrically coupled to first and second contact regions. A voltage difference is applied between the first and second contact regions. As a result, a current flows between the first and second contact regions in the electrically conducting region. The voltage difference and the materials of the electrically conducting region and the liner region are such that electromigration occurs only in the electrically conducting region. As a result, a void region within the electrically conducting region expands in the direction of the flow of the charged particles constituting the current. Because the resistor loses a conducting portion of the electrically conducting region to the void region, the resistance of the resistor is increased (i.e., tuned).

    摘要翻译： 电阻器结构及其调谐方法。 电阻器包括耦合到衬垫区域的导电区域。 导电区域和衬里区域都电耦合到第一和第二接触区域。 在第一和第二接触区域之间施加电压差。 结果，电流在导电区域中的第一和第二接触区域之间流动。 导电区域和衬垫区域的电压差和材料使得电迁移仅在导电区域中发生。 结果，导电区域内的空隙区域在构成电流的带电粒子的流动方向上膨胀。 因为电阻器将导电区域的导电部分损失到空隙区域，电阻器的电阻增加（即调谐）。

    METHOD OF FABRICATING A PRECISION BURIED RESISTOR
    2.
    发明申请
    METHOD OF FABRICATING A PRECISION BURIED RESISTOR 有权
    制造精密电阻器的方法

    公开(公告)号：US20070194390A1

    公开(公告)日：2007-08-23

    申请号：US11276282

    申请日：2006-02-22

    申请人： Anil Chinthakindi ,  Douglas Coolbaugh ,  Keith Downes ,  Ebenezer Eshun ,  John Florkey ,  Heidi Greer ,  Robert Rassel ,  Anthony Stamper ,  Kunal Vaed

    发明人： Anil Chinthakindi ,  Douglas Coolbaugh ,  Keith Downes ,  Ebenezer Eshun ,  John Florkey ,  Heidi Greer ,  Robert Rassel ,  Anthony Stamper ,  Kunal Vaed

    IPC分类号： H01L29/76

    CPC分类号： H01L29/8605 ,  H01L27/0802 ,  H01L28/20

    摘要： The present invention provides a semiconductor structure including a buried resistor with improved control, in which the resistor is fabricated in a region of a semiconductor substrate beneath a well region that is also present in the substrate. In accordance with the present invention, the inventive structure includes a semiconductor substrate containing at least a well region; and a buried resistor located in a region of the semiconductor substrate that is beneath said well region. The present invention also provides a method of fabricating such a structure in which a deep ion implantation process is used to form the buried resistor and a shallower ion implantation process is used in forming the well region.

    摘要翻译： 本发明提供一种包括具有改进控制的掩埋电阻器的半导体结构，其中电阻器制造在半导体衬底的也存在于衬底中的阱区域下方的区域中。 根据本发明，本发明的结构包括至少含有一个阱区的半导体衬底; 以及位于半导体衬底的位于所述阱区之下的区域中的掩埋电阻器。 本发明还提供一种制造这样的结构的方法，其中使用深离子注入工艺来形成掩埋电阻器，并且在形成阱区域中使用较浅的离子注入工艺。

    RESISTOR TUNING
    5.
    发明申请
    RESISTOR TUNING 审中-公开
    电阻调谐

    公开(公告)号：US20070187800A1

    公开(公告)日：2007-08-16

    申请号：US11737304

    申请日：2007-04-19

    申请人： Douglas Coolbaugh ,  Ebenezer Eshun ,  Robert Rassel ,  Anthony Stamper

    发明人： Douglas Coolbaugh ,  Ebenezer Eshun ,  Robert Rassel ,  Anthony Stamper

    IPC分类号： H01L29/00 ,  H01L21/20

    CPC分类号： H01C17/267

    摘要： A structure for resistors and the method for tuning the same. The resistor comprises an electrically conducting region coupled to a liner region. Both the electrically conducting region and the liner region are electrically coupled to first and second contact regions. A voltage difference is applied between the first and second contact regions. As a result, a current flows between the first and second contact regions in the electrically conducting region. The voltage difference and the materials of the electrically conducting region and the liner region are such that electromigration occurs only in the electrically conducting region. As a result, a void region within the electrically conducting region expands in the direction of the flow of the charged particles constituting the current. Because the resistor loses a conducting portion of the electrically conducting region to the void region, the resistance of the resistor is increased (i.e., tuned).

    摘要翻译： 电阻器结构及其调谐方法。 电阻器包括耦合到衬垫区域的导电区域。 导电区域和衬里区域都电耦合到第一和第二接触区域。 在第一和第二接触区域之间施加电压差。 结果，电流在导电区域中的第一和第二接触区域之间流动。 导电区域和衬垫区域的电压差和材料使得电迁移仅在导电区域中发生。 结果，导电区域内的空隙区域在构成电流的带电粒子的流动方向上膨胀。 因为电阻器将导电区域的导电部分损失到空隙区域，电阻器的电阻增加（即调谐）。

    PROCESS FOR SINGLE AND MULTIPLE LEVEL METAL-INSULATOR-METAL INTEGRATION WITH A SINGLE MASK
    6.
    发明申请
    PROCESS FOR SINGLE AND MULTIPLE LEVEL METAL-INSULATOR-METAL INTEGRATION WITH A SINGLE MASK 有权
    单层和多层金属绝缘子 - 金属整合与单面蒙皮的工艺

    公开(公告)号：US20070065966A1

    公开(公告)日：2007-03-22

    申请号：US11162661

    申请日：2005-09-19

    申请人： Anil Chinthakindi ,  Douglas Coolbaugh ,  Keith Downes ,  Ebenezer Eshun ,  Zhong-Xiang He ,  Robert Rassel ,  Anthony Stamper

    发明人： Anil Chinthakindi ,  Douglas Coolbaugh ,  Keith Downes ,  Ebenezer Eshun ,  Zhong-Xiang He ,  Robert Rassel ,  Anthony Stamper

    IPC分类号： H01L21/00 ,  H01L29/84

    CPC分类号： H01L21/32139 ,  H01L21/32136 ,  H01L28/75

    摘要： Method of fabricating a MIM capacitor and MIM capacitor. The method includes providing a substrate including a dielectric layer formed on a first conductive layer and a second conductive layer formed over the dielectric layer, and patterning a mask on the second conductive layer. Exposed portions of the second conductive layer are removed to form an upper plate of a MIM capacitor having edges substantially aligned with respective edges of the mask. The upper plate is undercut so that edges of the upper plate are located under the mask. Exposed portions of the dielectric layer and the first conductive layer are removed using the mask to form a capacitor dielectric layer and a lower plate of the MIM capacitor having edges substantially aligned with respective edges of the mask.

    摘要翻译： 制造MIM电容器和MIM电容器的方法。 该方法包括提供包括形成在第一导电层上的电介质层和形成在电介质层上的第二导电层的衬底，以及在第二导电层上构图掩模。 去除第二导电层的暴露部分以形成具有与掩模的相应边缘基本对齐的边缘的MIM电容器的上板。 上板被切下，使得上板的边缘位于掩模下方。 使用掩模去除电介质层和第一导电层的暴露部分，以形成MIM电容器的电容器电介质层和具有基本上与掩模的各个边缘对准的边缘的MIM电容器的下板。

    INTEGRATION OF A MIM CAPACITOR OVER A METAL GATE OR SILICIDE WITH HIGH-K DIELECTRIC MATERIALS
    7.
    发明申请
    INTEGRATION OF A MIM CAPACITOR OVER A METAL GATE OR SILICIDE WITH HIGH-K DIELECTRIC MATERIALS 有权
    金属栅极或硅化物上的MIM电容器与高K电介质材料的集成

    公开(公告)号：US20070057343A1

    公开(公告)日：2007-03-15

    申请号：US11162471

    申请日：2005-09-12

    申请人： Anil Chinthakindi ,  Douglas Coolbaugh ,  Keith Downes ,  Ebenezer Eshun ,  Zhong-Xiang He ,  Robert Rassel ,  Anthony Stamper ,  Kunal Vaed

    发明人： Anil Chinthakindi ,  Douglas Coolbaugh ,  Keith Downes ,  Ebenezer Eshun ,  Zhong-Xiang He ,  Robert Rassel ,  Anthony Stamper ,  Kunal Vaed

    IPC分类号： H01L29/00

    CPC分类号： H01L28/40

    摘要： A Metal Insulator-Metal (MIM) capacitor is formed on a semiconductor substrate with a base comprising a semiconductor substrate having a top surface and including regions formed in the surface selected from a Shallow Trench Isolation (STI) region and a doped well having exterior surfaces coplanar with the semiconductor substrate. An ancillary MIM capacitor plate is selected either a lower electrode formed on the STI region in the semiconductor substrate or a doped well formed in the top surface of the semiconductor substrate. A capacitor HiK dielectric layer is formed on or above the MIM capacitor lower plate. A second MIM capacitor plate is formed on the HiK dielectric layer above the MIM capacitor lower plate.

    摘要翻译： 金属绝缘体 - 金属（MIM）电容器形成在半导体衬底上，其基底包括具有顶表面的半导体衬底，并且包括形成在从浅沟槽隔离（STI）区域中形成的区域和具有外表面的掺杂阱 与半导体衬底共面。 辅助MIM电容器板选择形成在半导体衬底中的STI区域上的下电极或形成在半导体衬底的顶表面中的掺杂阱。 在MIM电容器下板上形成电容器HiK电介质层。 在MIM电容器下板上方的HiK电介质层上形成第二MIM电容器板。

    HEAT SINK FOR INTEGRATED CIRCUIT DEVICES
    9.
    发明申请
    HEAT SINK FOR INTEGRATED CIRCUIT DEVICES 有权
    集成电路设备的散热

    公开(公告)号：US20060152333A1

    公开(公告)日：2006-07-13

    申请号：US10905546

    申请日：2005-01-10

    申请人： Douglas Coolbaugh ,  Ebenezer Eshun ,  Terence Hook ,  Robert Rassel ,  Edmund Sprogis ,  Anthony Stamper ,  William Murphy

    发明人： Douglas Coolbaugh ,  Ebenezer Eshun ,  Terence Hook ,  Robert Rassel ,  Edmund Sprogis ,  Anthony Stamper ,  William Murphy

    IPC分类号： H01C1/08

    CPC分类号： H01C7/1013 ,  H01C1/084 ,  H01L2924/0002 ,  Y10T29/49083 ,  Y10T29/49085 ,  Y10T29/49099 ,  Y10T29/49144 ,  Y10T29/49147 ,  H01L2924/00

    摘要： A resistor with heat sink is provided. The heat sink includes a conductive path having metal or other thermal conductor having a high thermal conductivity. To avoid shorting the electrical resistor to ground with the thermal conductor, a thin layer of high thermal conductivity electrical insulator is interposed between the thermal conductor and the body of the resistor. Accordingly, a resistor can carry large amounts of current because the high conductivity thermal conductor will conduct heat away from the resistor to a heat sink. Various configurations of thermal conductors and heat sinks are provided offering good thermal conductive properties in addition to reduced parasitic capacitances and other parasitic electrical effects, which would reduce the high frequency response of the electrical resistor.

    摘要翻译： 提供带散热片的电阻。 散热器包括具有导热性高的金属或其它热导体的导电路径。 为了避免使用热导体将电阻器短路接地，在热导体和电阻体之间插入有一层薄导电电绝缘体。 因此，电阻器可承载大量的电流，因为高导电性热导体将热量从电阻器传导到散热器。 除了降低寄生电容和其他寄生电效应之外，提供各种配置的导热体和散热片，提供良好的导热性能，这将降低电阻器的高频响应。

    INTEGRATED THIN-FILM RESISTOR WITH DIRECT CONTACT
    10.
    发明申请
    INTEGRATED THIN-FILM RESISTOR WITH DIRECT CONTACT 有权
    集成薄膜电阻与直接接触

    公开(公告)号：US20070290272A1

    公开(公告)日：2007-12-20

    申请号：US11846595

    申请日：2007-08-29

    申请人： Eric Coker ,  Douglas Coolbaugh ,  Ebenezer Eshun ,  Zhong-Xiang He ,  Matthew Moon ,  Anthony Stamper

    发明人： Eric Coker ,  Douglas Coolbaugh ,  Ebenezer Eshun ,  Zhong-Xiang He ,  Matthew Moon ,  Anthony Stamper

    IPC分类号： H01L29/00

    CPC分类号： H01L27/016

    摘要： A BEOL thin-film resistor adapted for flexible integration rests on a first layer of ILD. The thickness of the first layer of ILD and the resistor thickness combine to match the nominal design thickness of vias in the layer of concern. A second layer of ILD matches the resistor thickness and is planarized to the top surface of the resistor. A third layer of ILD has a thickness equal to the nominal value of the interconnections on this layer. Dual damascene interconnection apertures and apertures for making contact with the resistor are formed simultaneously, with the etch stop upper cap layer in the resistor protecting the resistive layer while the vias in the dual damascene apertures are formed.

    摘要翻译： 适用于灵活集成的BEOL薄膜电阻依赖于第一层ILD。 ILD的第一层的厚度和电阻器厚度相结合，以匹配所涉及的层中的通孔的标称设计厚度。 第二层ILD匹配电阻器厚度，并平坦化到电阻器的顶表面。 ILD的第三层具有等于该层上互连的标称值的厚度。 同时形成用于与电阻器接触的双镶嵌互连孔和孔，电阻器中的蚀刻停止上盖层保护电阻层，同时形成双镶嵌孔中的通孔。