公开(公告)号：US20070181974A1

公开(公告)日：2007-08-09

申请号：US11307404

申请日：2006-02-06

申请人： Douglas Coolbaugh ,  Timothy Dalton ,  Daniel Edelstein ,  Ebenezer Eshun ,  Jeffrey Gambino ,  Kevin Petrarca ,  Anthony Stamper ,  Richard Volant

发明人： Douglas Coolbaugh ,  Timothy Dalton ,  Daniel Edelstein ,  Ebenezer Eshun ,  Jeffrey Gambino ,  Kevin Petrarca ,  Anthony Stamper ,  Richard Volant

IPC分类号： H01L29/00 ,  H01L21/20

CPC分类号： H01L28/20 ,  H01L23/5228 ,  H01L23/53238 ,  H01L23/53295 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

摘要： Resistors that avoid the problems of miniaturization of semiconductor devices and a related method are disclosed. In one embodiment, a resistor includes a planar resistor material that extends vertically within at least one metal layer of a semiconductor device. In another embodiment, a resistor includes a resistor material layer extending between a first bond pad and a second bond pad of a semiconductor device. The two embodiments can be used alone or together. A related method for generating the resistors is also disclosed.

摘要翻译： 公开了避免半导体器件小型化的问题的电阻器及相关方法。 在一个实施例中，电阻器包括在半导体器件的至少一个金属层内垂直延伸的平面电阻器材料。 在另一个实施例中，电阻器包括在半导体器件的第一接合焊盘和第二接合焊盘之间延伸的电阻材料层。 这两个实施方案可以单独使用或一起使用。 还公开了用于产生电阻器的相关方法。

公开(公告)号：US20080090407A1

公开(公告)日：2008-04-17

申请号：US11953927

申请日：2007-12-11

申请人： Douglas Coolbaugh ,  Daniel Edelstein ,  Ebenezer Eshun ,  Zhong-Xiang He ,  Robert Rassel ,  Anthony Stamper

发明人： Douglas Coolbaugh ,  Daniel Edelstein ,  Ebenezer Eshun ,  Zhong-Xiang He ,  Robert Rassel ,  Anthony Stamper

IPC分类号： H01L21/44

CPC分类号： H01L24/11 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05007 ,  H01L2224/05022 ,  H01L2224/05554 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2224/45124 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/05552

摘要： Terminal pads and methods of fabricating terminal pads. The methods including forming a conductive diffusion barrier under a conductive pad in or overlapped by a passivation layer comprised of multiple dielectric layers including diffusion barrier layers. The methods including forming the terminal pads subtractively or by a damascene process.

摘要翻译： 端子焊盘和制造端子焊盘的方法。 所述方法包括在由包括扩散阻挡层的多个电介质层组成的钝化层的内部或与其重叠的导电焊盘下方形成导电扩散阻挡层。 所述方法包括减法地形成端子焊盘或通过镶嵌工艺。

公开(公告)号：US20060249848A1

公开(公告)日：2006-11-09

申请号：US10908346

申请日：2005-05-09

申请人： Douglas Coolbaugh ,  Daniel Edelstein ,  Ebenezer Eshun ,  Zhong-Xiang He ,  Robert Rassel ,  Anthony Stamper

发明人： Douglas Coolbaugh ,  Daniel Edelstein ,  Ebenezer Eshun ,  Zhong-Xiang He ,  Robert Rassel ,  Anthony Stamper

IPC分类号： B32B7/12

CPC分类号： H01L24/11 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05007 ,  H01L2224/05022 ,  H01L2224/05554 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2224/45124 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/05552

摘要： Terminal pads and methods of fabricating terminal pads. The methods including forming a conductive diffusion barrier under a conductive pad in or overlapped by a passivation layer comprised of multiple dielectric layers including diffusion barrier layers. The methods including forming the terminal pads subtractively or by a damascene process.

公开(公告)号：US20050167838A1

公开(公告)日：2005-08-04

申请号：US10707996

申请日：2004-01-30

申请人： Daniel Edelstein ,  Matthew Colburn ,  Edward Cooney ,  Timothy Dalton ,  John Fitzsimmons ,  Jeffrey Gambino ,  Elbert Huang ,  Michael Lane ,  Vincent McGahay ,  Lee Nicholson ,  Satyanarayana Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas Shaw ,  Andrew Simon ,  Anthony Stamper

发明人： Daniel Edelstein ,  Matthew Colburn ,  Edward Cooney ,  Timothy Dalton ,  John Fitzsimmons ,  Jeffrey Gambino ,  Elbert Huang ,  Michael Lane ,  Vincent McGahay ,  Lee Nicholson ,  Satyanarayana Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas Shaw ,  Andrew Simon ,  Anthony Stamper

IPC分类号： H01L21/033 ,  H01L21/302 ,  H01L21/311 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L23/532 ,  H01L29/40

CPC分类号： B82Y30/00 ,  H01L21/0332 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

摘要： A method for manufacturing a structure includes providing a structure having an insulator layer with at least one interconnect and forming a sub lithographic template mask on the insulator layer. A selective etching step is used for etching the insulator layer through the sub lithographic template mask to form sub lithographic features near the at least one interconnect. A supra lithographic blocking mask may also be utilized. In another aspect, the method includes forming pinch off sections of sub lithographic size formed in a capping layer on the insulator layer. A semiconductor structure includes an insulator layer having at least one interconnect feature and at least one column formed in the insulator layer. A plurality of sub lithographic features formed on a top portion of the insulator layer and communicating with the at least one column is also provided. The plurality of sub lithographic features have a cross section or diameter less than any of the at least one column. A gap may be prohibited from forming on or near scribe lanes and vias

摘要翻译： 一种制造结构的方法包括提供具有至少一个互连的绝缘层的结构，并在绝缘体层上形成次光刻模板掩模。 选择性蚀刻步骤用于通过子光刻模板掩模蚀刻绝缘体层，以在至少一个互连附近形成亚光刻特征。 还可以使用超光刻阻挡掩模。 另一方面，该方法包括形成在绝缘体层上的覆盖层中形成的亚光刻尺寸的夹断部分。 半导体结构包括具有至少一个互连特征的绝缘体层和形成在绝缘体层中的至少一个列。 还提供了形成在绝缘体层的顶部并与至少一个柱连通的多个次级光刻特征。 所述多个亚光刻特征具有小于或小于所述至少一列中的任何一个的横截面或直径。 可能禁止在划线车道和通道上或附近形成间隙

公开(公告)号：US20050167780A1

公开(公告)日：2005-08-04

申请号：US10768773

申请日：2004-01-29

申请人： Daniel Edelstein ,  Panayotis Andricacos ,  John Cotte ,  Hariklia Deligianni ,  John Magerlein ,  Kevin Petrarca ,  Kenneth Stein ,  Richard Volant

发明人： Daniel Edelstein ,  Panayotis Andricacos ,  John Cotte ,  Hariklia Deligianni ,  John Magerlein ,  Kevin Petrarca ,  Kenneth Stein ,  Richard Volant

IPC分类号： H01F41/04 ,  H01F17/00 ,  H01L21/02 ,  H01L23/485 ,  H01L23/522 ,  H01L23/532 ,  H01L27/08 ,  H01L23/48 ,  H01L21/8222

CPC分类号： H01L24/12 ,  H01L23/5227 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L27/08 ,  H01L28/10 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05007 ,  H01L2224/05014 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05084 ,  H01L2224/05555 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48724 ,  H01L2224/48744 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00

摘要： An inductor and a method of forming and the inductor, the method including: (a) providing a semiconductor substrate; (b) forming a dielectric layer on a top surface of the substrate; (c) forming a lower trench in the dielectric layer; (d) forming a resist layer on a top surface of the dielectric layer; (e) forming an upper trench in the resist layer, the upper trench aligned to the lower trench, a bottom of the upper trench open to the lower trench; and (f) completely filling the lower trench at least partially filling the upper trench with a conductor in order to form the inductor. The inductor including a top surface, a bottom surface and sidewalls, a lower portion of said inductor extending a fixed distance into a dielectric layer formed on a semiconductor substrate and an upper portion extending above said dielectric layer; and means to electrically contact said inductor.

摘要翻译： 一种电感器及其形成方法和电感器，所述方法包括：（a）提供半导体衬底; （b）在所述基板的顶表面上形成电介质层; （c）在介电层中形成下沟槽; （d）在介电层的顶表面上形成抗蚀剂层; （e）在所述抗蚀剂层中形成上沟槽，所述上沟槽对准所述下沟槽，所述上沟槽的底部通向所述下沟槽; 和（f）用导体完全填充下沟槽至少部分地填充上沟槽，以形成电感器。 所述电感器包括顶表面，底表面和侧壁，所述电感器的下部将固定距离延伸到形成在半导体衬底上的电介质层和在所述电介质层上方延伸的上部; 以及用于电接触所述电感器的装置。

公开(公告)号：US20060105534A1

公开(公告)日：2006-05-18

申请号：US11320375

申请日：2005-12-28

申请人： Daniel Edelstein ,  Panayotis Andricacos ,  John Cotte ,  Hariklia Deligianni ,  John Magerlein ,  Kevin Petrarca ,  Kenneth Stein ,  Richard Volant

发明人： Daniel Edelstein ,  Panayotis Andricacos ,  John Cotte ,  Hariklia Deligianni ,  John Magerlein ,  Kevin Petrarca ,  Kenneth Stein ,  Richard Volant

IPC分类号： H01L21/8222

CPC分类号： H01L24/12 ,  H01L23/5227 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L27/08 ,  H01L28/10 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05007 ,  H01L2224/05014 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05084 ,  H01L2224/05555 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48724 ,  H01L2224/48744 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00

摘要： An inductor and a method of forming and the inductor, the method including: (a) forming a dielectric layer on a top surface of a substrate; (b) forming a lower trench in the dielectric layer; (c) forming a resist layer on a top surface of the dielectric layer; (d) forming an upper trench in the resist layer, the upper trench aligned to the lower trench, a bottom of the upper trench open to the lower trench; and (e) completely filling the lower trench at least partially filling the upper trench with a conductor in order to form the inductor. The inductor including a top surface, a bottom surface and sidewalls, a lower portion of said inductor extending a fixed distance into a dielectric layer formed on a semiconductor substrate and an upper portion extending above said dielectric layer; and means to electrically contact said inductor.

摘要翻译： 一种电感器及其形成方法和电感器，所述方法包括：（a）在基板的顶表面上形成电介质层; （b）在介电层中形成下沟槽; （c）在介电层的顶表面上形成抗蚀剂层; （d）在抗蚀剂层中形成上沟槽，上沟槽与下沟槽对准，上沟槽的底部通向下沟槽; 和（e）用导体完全填充下沟槽至少部分地填充上沟槽，以形成电感器。 所述电感器包括顶表面，底表面和侧壁，所述电感器的下部将固定距离延伸到形成在半导体衬底上的电介质层和在所述电介质层上方延伸的上部; 以及用于电接触所述电感器的装置。

公开(公告)号：US20080020230A1

公开(公告)日：2008-01-24

申请号：US11865215

申请日：2007-10-01

申请人： Daniel Edelstein ,  Edward Cooney ,  John Fitzsimmons ,  Jeffrey Gambino ,  Anthony Stamper

发明人： Daniel Edelstein ,  Edward Cooney ,  John Fitzsimmons ,  Jeffrey Gambino ,  Anthony Stamper

IPC分类号： B32B15/00 ,  B05D1/36

CPC分类号： H01L23/53238 ,  H01L23/5226 ,  H01L2924/0002 ,  Y10T428/12493 ,  H01L2924/00

摘要： Improved mechanical and adhesive strength and resistance to breakage of copper integrated circuit interconnections is obtained by forming a copper alloy in a copper via/wiring connection in an integrated circuit while minimizing adverse electrical effects of the alloy by confining the alloy to an interfacial region of said via/wiring connection and not elsewhere by a barrier which reduces or substantially eliminates the thickness of alloy in the conduction path. The alloy location and composition are further stabilized by reaction of all available alloying material with copper, copper alloys or other metals and their alloys.

摘要翻译： 通过在集成电路中的铜通孔/布线连接中形成铜合金，同时通过将合金限制在所述合金的界面区域来最小化合金的不利电效应来获得铜集成电路互连的改进的机械和粘合强度和断裂性 通孔/布线连接，而不在其他地方，通过减小或基本消除导电路径中合金的厚度。 通过所有可用的合金材料与铜，铜合金或其他金属及其合金的反应，合金位置和组成进一步稳定。

公开(公告)号：US20060027930A1

公开(公告)日：2006-02-09

申请号：US10710828

申请日：2004-08-05

申请人： Daniel Edelstein ,  Edward Cooney, III ,  John Fitzsimmons ,  Jeffrey Gambino ,  Anthony Stamper

发明人： Daniel Edelstein ,  Edward Cooney, III ,  John Fitzsimmons ,  Jeffrey Gambino ,  Anthony Stamper

IPC分类号： H01L23/48

CPC分类号： H01L23/53238 ,  H01L23/5226 ,  H01L2924/0002 ,  Y10T428/12493 ,  H01L2924/00

摘要： Improved mechanical and adhesive strength and resistance to breakage of copper integrated circuit interconnections is obtained by forming a copper alloy in a copper via/wiring connection in an integrated circuit while minimizing adverse electrical effects of the alloy by confining the alloy to an interfacial region of said via/wiring connection and not elsewhere by a barrier which reduces or substantially eliminates the thickness of alloy in the conduction path. The alloy location and composition are further stabilized by reaction of all available alloying material with copper, copper alloys or other metals and their alloys.

摘要翻译： 通过在集成电路中的铜通孔/布线连接中形成铜合金，同时通过将合金限制在所述合金的界面区域来最小化合金的不利电效应来获得铜集成电路互连的改进的机械和粘合强度和断裂性 通孔/布线连接，而不在其他地方，通过减小或基本消除导电路径中合金的厚度。 通过所有可用的合金材料与铜，铜合金或其他金属及其合金的反应，合金位置和组成进一步稳定。

公开(公告)号：US20050098605A1

公开(公告)日：2005-05-12

申请号：US10702416

申请日：2003-11-06

申请人： Daniel Edelstein ,  John Fitzsimmons ,  Jeffrey Gambino ,  Anthony Stamper

发明人： Daniel Edelstein ,  John Fitzsimmons ,  Jeffrey Gambino ,  Anthony Stamper

IPC分类号： B23K20/00 ,  H01L23/485 ,  B23K37/00

CPC分类号： H01L24/85 ,  B23K20/007 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48463 ,  H01L2224/48609 ,  H01L2224/48611 ,  H01L2224/48644 ,  H01L2224/48709 ,  H01L2224/48711 ,  H01L2224/48744 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85359 ,  H01L2224/85801 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/01049 ,  H01L2924/00 ,  H01L2924/00015

摘要： A structure and method for low-pressure wirebonding, reducing the propensity of dielectric material to mechanical failure due to wirebond stress. A low temperature alloy on the surface of a bond pad allows alloy bond formation to occur between the wire and the bond pad at reduced bond pressures and reduced thermal and ultrasonic energies. Preferred alloys include Au—Sn and Au—In. The Au—Sn alloy may be formed over the Cu bond pad, incorporated in an aluminum bond pad stack, or deposited on a bond pad having Ni—Au capping of Cu or Al bond pads.

摘要翻译： 一种用于低压引线键合的结构和方法，降低了由于引线键应力导致的介电材料对机械故障的倾向。 接合焊盘表面上的低温合金允许在降低的接合压力和降低的热和超声能量的情况下在导线和接合焊盘之间形成合金结合。 优选的合金包括Au-Sn和Au-In。 Au-Sn合金可以形成在结合在铝焊盘叠层中的Cu焊盘上，或者沉积在具有Cu或Al键合焊盘的Ni-Au封盖的焊盘上。

公开(公告)号：US20060183062A1

公开(公告)日：2006-08-17

申请号：US10906268

申请日：2005-02-11

申请人： Christos Dimitrakopoulos ,  Daniel Edelstein ,  Vincent McGahay ,  Satyanarayana Nitta ,  Kevin Petrarca ,  Shom Ponoth ,  Shahab Siddiqui

发明人： Christos Dimitrakopoulos ,  Daniel Edelstein ,  Vincent McGahay ,  Satyanarayana Nitta ,  Kevin Petrarca ,  Shom Ponoth ,  Shahab Siddiqui

IPC分类号： G03F7/00

CPC分类号： G03F7/2022

摘要： A method of selectively altering material properties of a substrate in one region while making a different alteration of material properties in an adjoining region is provided. The method includes selectively masking a first portion of the substrate during a first exposure and selectively masking a second portion of the substrate during a second exposure. Additionally, a mask may be formed having more than one thickness where each thickness will selectively reduce the amount of energy from a blanket exposure of the substrate thereby allowing a substrate to receive different levels of energy dosage in a single blanket exposure.

摘要翻译： 提供了一种在邻接区域中对材料性质进行不同的改变的同时选择性地改变一个区域中的衬底的材料特性的方法。 该方法包括在第一曝光期间选择性地掩蔽衬底的第一部分，并且在第二次曝光期间选择性地掩蔽衬底的第二部分。 另外，可以形成具有多于一个厚度的掩模，其中每个厚度将选择性地减少来自衬底的覆盖曝光的能量的量，从而允许衬底在单次覆盖曝光中接收不同水平的能量。