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1.发明授权Design structure with a deep sub-collector, a reach-through structure and trench isolation 有权具有深子集电极的设计结构，通孔结构和沟槽隔离公开(公告)号：US08015538B2
公开(公告)日：2011-09-06
申请号：US11941104
申请日：2007-11-16
CPC分类号： H01L29/0821 , H01L29/66272
摘要： The invention relates to noise isolation in semiconductor devices, and a design structure on which a subject circuit resides. A design structure is embodied in a machine readable medium used in a design process. The design structure includes a deep sub-collector located in a first epitaxial layer, and a doped region located in a second epitaxial layer, which is above the first epitaxial layer. The design structure further includes a reach-through structure penetrating from a surface of the device through the first and second epitaxial layers to the deep sub-collector, and a trench isolation structure penetrating from a surface of the device and surrounding the doped region.
摘要翻译： 本发明涉及半导体器件中的噪声隔离以及被摄体电路所在的设计结构。 设计结构体现在在设计过程中使用的机器可读介质中。 该设计结构包括位于第一外延层中的深子集电极和位于第一外延层之上的第二外延层中的掺杂区域。 该设计结构进一步包括从装置的表面穿过第一外延层和第二外延层到达深亚集电体的通孔结构，以及从该器件的表面穿透且围绕掺杂区域的沟槽隔离结构。
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公开(公告)号：US20080087978A1
公开(公告)日：2008-04-17
申请号：US11548310
申请日：2006-10-11
CPC分类号： H01L29/0821 , H01L21/743 , H01L21/8249 , H01L27/0251 , H01L29/66242 , H01L29/737 , H01L29/78
摘要： A structure and method comprises a deep sub-collector located in a first epitaxial layer and a doped region located in a second epitaxial layer, which is above the first epitaxial layer. The device further comprises a reach-through structure penetrating from a surface of the device through the first and second epitaxial layers to the deep sub-collector, and a trench isolation structure penetrating from a surface of the device and surrounding the doped region.
摘要翻译： 一种结构和方法包括位于第一外延层中的深子集电极和位于第一外延层之上的第二外延层中的掺杂区。 该器件还包括从器件的表面穿过第一和第二外延层到达深子集电极的通孔结构，以及从器件的表面穿透且围绕掺杂区域的沟槽隔离结构。
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公开(公告)号：US20080092094A1
公开(公告)日：2008-04-17
申请号：US11941104
申请日：2007-11-16
IPC分类号： G06F17/50
CPC分类号： H01L29/0821 , H01L29/66272
摘要： The invention relates to noise isolation in semiconductor devices, and a design structure on which a subject circuit resides. A design structure is embodied in a machine readable medium used in a design process. The design structure includes a deep sub-collector located in a first epitaxial layer, and a doped region located in a second epitaxial layer, which is above the first epitaxial layer. The design structure further includes a reach-through structure penetrating from a surface of the device through the first and second epitaxial layers to the deep sub-collector, and a trench isolation structure penetrating from a surface of the device and surrounding the doped region.
摘要翻译： 本发明涉及半导体器件中的噪声隔离以及被摄体电路所在的设计结构。 设计结构体现在在设计过程中使用的机器可读介质中。 该设计结构包括位于第一外延层中的深子集电极和位于第一外延层之上的第二外延层中的掺杂区域。 该设计结构进一步包括从装置的表面穿过第一外延层和第二外延层到达深亚集电体的通孔结构，以及从该器件的表面穿透且围绕掺杂区域的沟槽隔离结构。
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公开(公告)号：US08338265B2
公开(公告)日：2012-12-25
申请号：US12269069
申请日：2008-11-12
申请人： Douglas D. Coolbaugh , Jeffrey B. Johnson , Peter J. Lindgren , Xuefeng Liu , James S. Nakos , Bradley A. Orner , Robert M. Rassel , David C. Sheridan
发明人： Douglas D. Coolbaugh , Jeffrey B. Johnson , Peter J. Lindgren , Xuefeng Liu , James S. Nakos , Bradley A. Orner , Robert M. Rassel , David C. Sheridan
IPC分类号： H01L21/76
CPC分类号： H01L21/743 , H01L21/28518 , H01L21/76224 , H01L21/8249 , H01L27/0623 , H01L29/41 , H01L2924/0002 , H01L2924/00
摘要： A trench contact silicide is formed on an inner wall of a contact trench that reaches to a buried conductive layer in a semiconductor substrate to reduce parasitic resistance of a reachthrough structure. The trench contact silicide is formed at the bottom, on the sidewalls of the trench, and on a portion of the top surface of the semiconductor substrate. The trench is subsequently filled with a middle-of-line (MOL) dielectric. A contact via may be formed on the trench contact silicide. The trench contact silicide may be formed through a single silicidation reaction with a metal layer or through multiple silicidation reactions with multiple metal layers.
摘要翻译： 沟槽接触硅化物形成在接触沟槽的内壁上，该接触沟槽的内壁到达半导体衬底中的掩埋导电层，以减小通孔结构的寄生电阻。 沟槽接触硅化物形成在底部，沟槽的侧壁上以及在半导体衬底的顶表面的一部分上。 沟槽随后填充有中间线（MOL）电介质。 可以在沟槽接触硅化物上形成接触通孔。 沟槽接触硅化物可以通过与金属层的单一硅化反应或通过与多个金属层的多次硅化反应形成。
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公开(公告)号：US20100117237A1
公开(公告)日：2010-05-13
申请号：US12269069
申请日：2008-11-12
申请人： Douglas D. Coolbaugh , Jeffrey B. Johnson , Peter J. Lindgren , Xuefeng Liu , James S. Nakos , Bradley A. Orner , Robert M. Rassel , David C. Sheridan
发明人： Douglas D. Coolbaugh , Jeffrey B. Johnson , Peter J. Lindgren , Xuefeng Liu , James S. Nakos , Bradley A. Orner , Robert M. Rassel , David C. Sheridan
CPC分类号： H01L21/743 , H01L21/28518 , H01L21/76224 , H01L21/8249 , H01L27/0623 , H01L29/41 , H01L2924/0002 , H01L2924/00
摘要： A trench contact silicide is formed on an inner wall of a contact trench that reaches to a buried conductive layer in a semiconductor substrate to reduce parasitic resistance of a reachthrough structure. The trench contact silicide is formed at the bottom, on the sidewalls of the trench, and on a portion of the top surface of the semiconductor substrate. The trench is subsequently filled with a middle-of-line (MOL) dielectric. A contact via may be formed on the trench contact silicide. The trench contact silicide may be formed through a single silicidation reaction with a metal layer or through multiple silicidation reactions with multiple metal layers.
摘要翻译： 沟槽接触硅化物形成在接触沟槽的内壁上，该接触沟槽的内壁到达半导体衬底中的掩埋导电层，以减小通孔结构的寄生电阻。 沟槽接触硅化物形成在底部，沟槽的侧壁上以及在半导体衬底的顶表面的一部分上。 沟槽随后填充有中间线（MOL）电介质。 可以在沟槽接触硅化物上形成接触通孔。 沟槽接触硅化物可以通过与金属层的单一硅化反应或通过与多个金属层的多次硅化反应形成。
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公开(公告)号：US07491632B2
公开(公告)日：2009-02-17
申请号：US11164108
申请日：2005-11-10
IPC分类号： H01L21/425
CPC分类号： H01L21/8249 , H01L29/0821 , H01L29/66272
摘要： A method of fabricating a buried subcollector in which the buried subcollector is implanted to a depth in which during subsequent epi growth the buried subcollector remains substantially below the fictitious interface between the epi layer and the substrate is provided. In particular, the inventive method forms a buried subcollector having an upper surface (i.e., junction) that is located at a depth from about 3000 Å or greater from the upper surface of the semiconductor substrate. This deep buried subcollector having an upper surface that is located at a depth from about 3000 Å or greater from the upper surface of the substrate is formed using a reduced implant energy (as compared to a standard deep implanted subcollector process) at a relative high dose. The present invention also provides a semiconductor structure including the inventive buried subcollector which can be used as cathode for passive devices in high frequency applications.
摘要翻译： 一种制造掩埋子集电极的方法，其中将埋入的子集电极注入深度，其中在随后的外延生长期间，掩埋子集电极基本上保持在外延层和衬底之间的虚拟界面的下方。 特别地，本发明的方法形成了具有从半导体衬底的上表面位于距离大约或更大的深度的上表面（即结）的掩埋子集电极。 该深埋底部集电器具有从衬底的上表面位于距离大约等于或更大的深度的上表面，其使用相对高剂量的减少的注入能量（与标准深度植入子集电极过程相比） 。 本发明还提供了一种半导体结构，其包括本发明的掩埋子集电极，其可以用作高频应用中的无源器件的阴极。
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公开(公告)号：US20140239498A1
公开(公告)日：2014-08-28
申请号：US13570737
申请日：2012-08-09
申请人： Douglas D. Coolbaugh , Jeffrey B. Johnson , Peter J. Lindgren , Xuefeng Liu , James S. Nakos , Bradley A. Orner , Robert M. Rassel , David C. Sheridan
发明人： Douglas D. Coolbaugh , Jeffrey B. Johnson , Peter J. Lindgren , Xuefeng Liu , James S. Nakos , Bradley A. Orner , Robert M. Rassel , David C. Sheridan
IPC分类号： H01L23/48 , H01L23/482
CPC分类号： H01L21/743 , H01L21/28518 , H01L21/76224 , H01L21/8249 , H01L27/0623 , H01L29/41 , H01L2924/0002 , H01L2924/00
摘要： A trench contact silicide is formed on an inner wall of a contact trench that reaches to a buried conductive layer in a semiconductor substrate to reduce parasitic resistance of a reachthrough structure. The trench contact silicide is formed at the bottom, on the sidewalls of the trench, and on a portion of the top surface of the semiconductor substrate. The trench is subsequently filled with a middle-of-line (MOL) dielectric. A contact via may be formed on the trench contact silicide. The trench contact silicide may be formed through a single silicidation reaction with a metal layer or through multiple silicidation reactions with multiple metal layers.
摘要翻译： 沟槽接触硅化物形成在接触沟槽的内壁上，该接触沟槽的内壁到达半导体衬底中的掩埋导电层，以减小通孔结构的寄生电阻。 沟槽接触硅化物形成在底部，沟槽的侧壁上以及在半导体衬底的顶表面的一部分上。 沟槽随后填充有中间线（MOL）电介质。 可以在沟槽接触硅化物上形成接触通孔。 沟槽接触硅化物可以通过与金属层的单一硅化反应或通过与多个金属层的多次硅化反应形成。
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公开(公告)号：US07691734B2
公开(公告)日：2010-04-06
申请号：US11680637
申请日：2007-03-01
IPC分类号： H01L21/04
CPC分类号： H01L21/763 , H01L29/0821 , H01L29/66272 , H01L29/732
摘要： A far subcollector, or a buried doped semiconductor layer located at a depth that exceeds the range of conventional ion implantation, is formed by ion implantation of dopants into a region of an initial semiconductor substrate followed by an epitaxial growth of semiconductor material. A reachthrough region to the far subcollector is formed by outdiffusing a dopant from a doped material layer deposited in the at least one deep trench that adjoins the far subcollector. The reachthrough region may be formed surrounding the at least one deep trench or only on one side of the at least one deep trench. If the inside of the at least one trench is electrically connected to the reachthrough region, a metal contact may be formed on the doped fill material within the at least one trench. If not, a metal contact is formed on a secondary reachthrough region that contacts the reachthrough region.
摘要翻译： 通过将掺杂剂离子注入到初始半导体衬底的区域中，随后半导体材料的外延生长，形成位于超过常规离子注入范围的深度的远的子集电极或掩埋掺杂半导体层。 通过从沉积在邻接远子集电极的至少一个深沟槽中的掺杂材料层向外扩散掺杂剂形成远子集电极的到达区域。 穿通区域可形成为围绕至少一个深沟槽或仅在至少一个深沟槽的一侧上。 如果至少一个沟槽的内部电连接到通孔区域，则可以在至少一个沟槽内的掺杂填充材料上形成金属接触。 如果不是，则在与接触区域接触的次级通过区域上形成金属接触。
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公开(公告)号：US20080211064A1
公开(公告)日：2008-09-04
申请号：US11680637
申请日：2007-03-01
IPC分类号： H01L29/06 , H01L21/425
CPC分类号： H01L21/763 , H01L29/0821 , H01L29/66272 , H01L29/732
摘要： A far subcollector, or a buried doped semiconductor layer located at a depth that exceeds the range of conventional ion implantation, is formed by ion implantation of dopants into a region of an initial semiconductor substrate followed by an epitaxial growth of semiconductor material. A reachthrough region to the far subcollector is formed by outdiffusing a dopant from a doped material layer deposited in the at least one deep trench that adjoins the far subcollector. The reachthrough region may be formed surrounding the at least one deep trench or only on one side of the at least one deep trench. If the inside of the at least one trench is electrically connected to the reachthrough region, a metal contact may be formed on the doped fill material within the at least one trench. If not, a metal contact is formed on a secondary reachthrough region that contacts the reachthrough region.
摘要翻译： 通过将掺杂剂离子注入到初始半导体衬底的区域中，随后半导体材料的外延生长，形成位于超过常规离子注入范围的深度的远的子集电极或掩埋掺杂半导体层。 通过从沉积在邻接远子集电极的至少一个深沟槽中的掺杂材料层向外扩散掺杂剂形成远子集电极的到达区域。 穿通区可以形成在至少一个深沟槽周围，或仅在至少一个深沟槽的一侧上。 如果至少一个沟槽的内部电连接到通孔区域，则可以在至少一个沟槽内的掺杂填充材料上形成金属接触。 如果不是，则在与接触区域接触的次级通过区域上形成金属接触。
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公开(公告)号：US08105924B2
公开(公告)日：2012-01-31
申请号：US12691320
申请日：2010-01-21
IPC分类号： H01L21/04
CPC分类号： H01L21/763 , H01L29/0821 , H01L29/66272 , H01L29/732
摘要： A far subcollector, or a buried doped semiconductor layer located at a depth that exceeds the range of conventional ion implantation, is formed by ion implantation of dopants into a region of an initial semiconductor substrate followed by an epitaxial growth of semiconductor material. A reachthrough region to the far subcollector is formed by outdiffusing a dopant from a doped material layer deposited in the at least one deep trench that adjoins the far subcollector. The reachthrough region may be formed surrounding the at least one deep trench or only on one side of the at least one deep trench. If the inside of the at least one trench is electrically connected to the reachthrough region, a metal contact may be formed on the doped fill material within the at least one trench. If not, a metal contact is formed on a secondary reachthrough region that contacts the reachthrough region.
摘要翻译： 通过将掺杂剂离子注入到初始半导体衬底的区域中，随后半导体材料的外延生长，形成位于超过常规离子注入范围的深度的远的子集电极或掩埋掺杂半导体层。 通过从沉积在邻接远子集电极的至少一个深沟槽中的掺杂材料层向外扩散掺杂剂形成远子集电极的到达区域。 穿通区域可形成为围绕至少一个深沟槽或仅在至少一个深沟槽的一侧上。 如果至少一个沟槽的内部电连接到通孔区域，则可以在至少一个沟槽内的掺杂填充材料上形成金属接触。 如果不是，则在与接触区域接触的次级通过区域上形成金属接触。
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