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公开(公告)号：US08020010B2
公开(公告)日：2011-09-13
申请号：US12144803
申请日：2008-06-24
CPC分类号： G06F1/3203 , G06F1/12 , G06F1/3225 , G06F1/3275 , G11C5/14 , G11C17/146 , G11C17/18 , Y02D10/14
摘要： A memory power controller comprises a clock generation circuitry for generating a first clock signal and a second clock signal responsive to a source clock and a determination that the source clock has a period greater than a predetermined value. The first clock is generated responsive to a determination that the source clock has a period greater than the predetermined value and the second clock is generated responsive to the determination that the source clock has a period less than the predetermined value. Memory time-out circuitry generates a memory enable/disable signal to control operation of an associated memory responsive to the clock signal and the determination that the source clock has a period greater than the predetermined value. The memory time-out circuitry further synchronizes the memory enable/disable signal with the source clock.
摘要翻译： 存储器功率控制器包括用于响应于源时钟产生第一时钟信号和第二时钟信号的时钟产生电路以及源时钟具有大于预定值的周期的确定。 响应于源时钟具有大于预定值的周期的确定产生第一时钟，并且响应于源时钟具有小于预定值的周期的确定而产生第二时钟。 存储器超时电路产生存储器使能/禁止信号，以响应于时钟信号来控制相关存储器的操作，以及确定源时钟具有大于预定值的周期。 存储器超时电路进一步使存储器使能/禁止信号与源时钟同步。
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公开(公告)号：US08010819B2
公开(公告)日：2011-08-30
申请号：US12255127
申请日：2008-10-21
申请人： Douglas F. Pastorello , Douglas Holberg , William Gene Durbin , Biranchinath Sahu , Golam R. Chowdhury
发明人： Douglas F. Pastorello , Douglas Holberg , William Gene Durbin , Biranchinath Sahu , Golam R. Chowdhury
CPC分类号： G06F1/3203 , H03K19/0016
摘要： A microcontroller unit includes a processor for generating a first control signal to start a comatose mode of operation for the microcontroller unit. Control logic responsive to the first control signal generates an enable signal at a first level and the control logic is further responsive to a second control signal for generating the enable signal at a second level. A voltage regulator generates regulated voltage from an input voltage. The voltage regulator shuts down to provide a zero volt regulated voltage responsive to the enable signal at the first level and powers up to provide a regulated voltage at an operating level responsive to the enable signal at the second level.
摘要翻译： 微控制器单元包括用于产生第一控制信号以开始微控制器单元的昏迷模式的处理器。 响应于第一控制信号的控制逻辑在第一电平产生使能信号，并且控制逻辑还响应于第二控制信号，以在第二电平产生使能信号。 电压调节器从输入电压产生调节电压。 电压调节器关闭，以响应于在第一电平的使能信号提供零伏调节电压，并且上电以响应于在第二电平的使能信号提供处于工作电平的调节电压。
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公开(公告)号：US06531906B2
公开(公告)日：2003-03-11
申请号：US10007588
申请日：2001-12-05
IPC分类号： H03H1126
CPC分类号： H03H17/0286 , H03H17/0036
摘要： A delay system includes a first filter configured for receiving a selected input signal and a first mechanism for activating the first filter to produce a delayed output signal which is a function of a selected input signal. The delay system further includes a second filter configured for receiving a signal from said first filter to apply an additional delay to the signal received by said first filter, and a second mechanism for activating the second filter to produce a delayed signal which is a function of a signal received from the first filter. The delay system further comprises a divider system for tracking times from a clock reference. The delay system implements a method of delaying a received signal by sampling a selected signal with a predetermined clock signal and producing the selected signal at a time delayed to the extent of a comparison of a reduced frequency clock with a predetermined value. The method further includes further delaying production of the selected signal with a second comparison utilizing a second predetermined value of a further reduced frequency clock.
摘要翻译： 延迟系统包括被配置为接收所选择的输入信号的第一滤波器和用于激活第一滤波器以产生作为所选输入信号的函数的延迟输出信号的第一机构。 所述延迟系统还包括第二滤波器，其被配置为从所述第一滤波器接收信号以对由所述第一滤波器接收的信号施加附加延迟;以及第二机构，用于激活所述第二滤波器以产生延迟信号，所述延迟信号是 从第一滤波器接收的信号。 延迟系统还包括用于跟踪来自时钟参考的时间的分频器系统。 延迟系统通过采用预定的时钟信号采样所选择的信号来实现延迟接收信号的方法，并且将延迟到缩小频率时钟与预定值的比较程度的时间产生所选择的信号。 该方法还包括进一步延迟所选择的信号的产生，并利用进一步降低的频率时钟的第二预定值进行第二比较。
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公开(公告)号：US5923273A
公开(公告)日：1999-07-13
申请号：US751708
申请日：1996-11-18
CPC分类号： H03H17/06 , H03H17/0226
摘要： A reduced power FIR filter may be utilized as the digital decimation filter for a delta sigma ADC. The FIR filter utilizes a serial bit stream which is part of the control path of the filter. Thus, operations of the circuitry which comprises the filter may be controlled depending upon the data presented at the output of the delta sigma modulator. In particular, filter operations may be enabled only for a given digital state, for example, a digital 1 state. Thus, the filter operations may be enabled only for typically half of the bits from the serial bit stream and the power usage of the digital filter is significantly reduced.
摘要翻译： 降低功率FIR滤波器可以用作Δ西格玛ADC的数字抽取滤波器。 FIR滤波器利用串行比特流，该比特流是滤波器的控制路径的一部分。 因此，可以根据呈现在Δ-Σ调制器的输出处的数据来控制包括滤波器的电路的操作。 特别地，可以仅针对给定的数字状态（例如，数字1状态）使能滤波器操作。 因此，滤波器操作可以仅来自串行比特流的典型的一半比特，并且数字滤波器的功率使用量显着降低。
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公开(公告)号：US07441131B2
公开(公告)日：2008-10-21
申请号：US11240923
申请日：2005-09-30
申请人： Douglas F. Pastorello , Douglas Holberg , William Gene Durbin , Biranchinath Sahu , Golam R. Chowdhury
发明人： Douglas F. Pastorello , Douglas Holberg , William Gene Durbin , Biranchinath Sahu , Golam R. Chowdhury
CPC分类号： G06F1/3203 , H03K19/0016
摘要： A microcontroller unit includes a processor for generating a first control signal to start a comatose mode of operation for the microcontroller unit. Control logic responsive to the first control signal generates an enable signal at a first level and the control logic is further responsive to a second control signal for generating the enable signal at a second level. A voltage regulator generates regulated voltage from an input voltage. The voltage regulator shuts down to provide a zero volt regulated voltage responsive to the enable signal at the first level and powers up to provide a regulated voltage at an operating level responsive to the enable signal at the second level.
摘要翻译： 微控制器单元包括用于产生第一控制信号以开始微控制器单元的昏迷模式的处理器。 响应于第一控制信号的控制逻辑在第一电平产生使能信号，并且控制逻辑还响应于第二控制信号，以在第二电平产生使能信号。 电压调节器从输入电压产生调节电压。 电压调节器关闭，以响应于在第一电平的使能信号提供零伏调节电压，并且上电以响应于在第二电平的使能信号提供处于工作电平的调节电压。
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公开(公告)号：US20080091992A1
公开(公告)日：2008-04-17
申请号：US11531832
申请日：2006-09-14
IPC分类号： G01R31/28
CPC分类号： G01R31/31713 , G01R1/0408 , G01R31/31701 , G01R31/318544
摘要： A technique for increasing functionality of terminals of an integrated circuit without increasing the number of terminals of the integrated circuit utilizes at least one tri-level terminal and converter circuit that provides a logic level indicative of a test mode of the integrated circuit in response to a corresponding input level. The technique substantially reduces or eliminates false detections of the test mode and substantially reduces or eliminates falsely enabling other (e.g., functional) mode(s) of the integrated circuit.
摘要翻译： 用于增加集成电路的终端的功能而不增加集成电路的终端数量的技术利用至少一个三电平终端和转换器电路，其提供指示集成电路的测试模式的逻辑电平，以响应于 相应的输入电平。 该技术基本上减少或消除了测试模式的错误检测，并且基本上减少或消除了错误地启用集成电路的其他（例如，功能）模式。
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公开(公告)号：US06557051B1
公开(公告)日：2003-04-29
申请号：US09484129
申请日：2000-01-15
IPC分类号： G06F1314
CPC分类号： G06F13/4291
摘要： A serial interface or port is configured so that: a Read command and a Write command can be performed substantially simultaneously; a shortened Read command, followed by another Read command, can be performed in reduced time, due to the shortening of the first Read command; and a continuous stream of Read commands can be performed consecutively with no time delay By performing Read and Write commands simultaneously on associated channels at a serial interface, the time required for such performance is reduced by as much as 50 percent.
摘要翻译： 串行接口或端口被配置为：可以基本上同时执行读命令和写命令; 由于缩短了第一个Read命令，缩短的Read命令后跟另一个Read命令可以在缩短的时间内执行; 并且可以连续执行连续的Read命令流，无需时间延迟通过在串行接口的相关通道上同时执行读写命令，这种性能所需的时间可减少多达50％。
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公开(公告)号：US07405601B2
公开(公告)日：2008-07-29
申请号：US11680026
申请日：2007-02-28
IPC分类号： H03K21/00
CPC分类号： H03K23/66 , H03K21/10 , H03L7/0805 , H03L7/087 , H03L7/091 , H03L7/093 , H03L7/193 , H03L7/1974 , H03L7/1976
摘要： In at least one embodiment of the invention, a method for dividing a first signal having a first frequency by a divide ratio to generate a lower frequency signal includes generating a first plurality of signals having a common frequency, a first pulse width, and different phases. The first plurality of signals is based, at least in part, on at least one signal having a second pulse width. The first pulse width is selected from a plurality of pulse widths based, at least in part, on the divide ratio. The method includes sequentially selecting individual pulses of the first plurality of signals as an output signal of a select circuit to generate an output signal having a frequency lower than the first frequency.
摘要翻译： 在本发明的至少一个实施例中，一种用于将具有第一频率的第一信号除以分频比以产生较低频率信号的方法包括产生具有共同频率，第一脉冲宽度和不同相位的第一多个信号 。 第一组多个信号至少部分地基于具有第二脉冲宽度的至少一个信号。 至少部分地基于分频比，从多个脉冲宽度中选择第一脉冲宽度。 该方法包括顺序选择第一多个信号中的各个脉冲作为选择电路的输出信号，以产生具有低于第一频率的频率的输出信号。
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公开(公告)号：US06487674B1
公开(公告)日：2002-11-26
申请号：US09521675
申请日：2000-03-08
IPC分类号： G06F104
摘要： A data clock pin SCLK may be used to receive an SCLK signal as well as sleep and reset signals. During normal operation, the SCLK input pin may receive the SCLK signal, a square wave type clock signal. However, the SCLK signal may also be coupled to a one-shot within the device. When signal SCLK is held high for a predetermined period of time, the one-shot is triggered and a SLEEP signal is generated. The device reacts to this SLEEP signal by entering a sleep mode. Similarly, if the SCLK signal is held low for a predetermined period of time, the one-shot may output a low level RESET signal. This RESET signal resets the device into an initial condition state. Other modes of operation, such as test modes and the like may be entered into by holding the SCLK signal high or low in conjunction with a predetermined logic level on another pin (e.g., VREF).
摘要翻译： 数据时钟引脚SCLK可用于接收SCLK信号以及睡眠和复位信号。 在正常工作期间，SCLK输入引脚可以接收SCLK信号，即方波型时钟信号。 然而，SCLK信号也可以耦合到设备内的单触发。 当信号SCLK保持高电平达预定时间时，触发单触发，并产生SLEEP信号。 该设备通过进入睡眠模式对此SLEEP信号做出反应。 类似地，如果SCLK信号在预定时间段内保持低电平，则单稳态可以输出低电平复位信号。 该RESET信号将器件复位为初始状态。 通过将SCLK信号与另一个引脚（例如，VREF）上的预定逻辑电平相结合保持高或低可以输入其他操作模式，例如测试模式等。
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公开(公告)号：US06377198B1
公开(公告)日：2002-04-23
申请号：US09596156
申请日：2000-03-20
IPC分类号： H03M300
CPC分类号： H03K17/6872 , H03K17/693
摘要： The present invention provides a method and apparatus to define and sustain such a physical level by connecting the output through a transmission gate to an input pin. For a certain state of the output, one level of an input may be fed through to the output to generate an output voltage level. In the preferred embodiment of the present invention, a chip select signal {overscore (CS)} is used to define a low level logic signal. An control logic selectively switches a high level logic signal voltage (e.g., V+supply voltage) or the low level logic signal voltage ({overscore (CS)}) to produce an output digital logic signal. In a further embodiment of the present invention, separate logic level signals INH and INL may be selectively switched by control logic to generate an output logic level signal independent of supply voltages V+ and V−.
摘要翻译： 本发明提供了一种通过将输出通过传输门连接到输入引脚来定义和维持这种物理水平的方法和装置。 对于输出的某一状态，可以将一个输入电平馈送到输出以产生输出电压电平。 在本发明的优选实施例中，使用芯片选择信号{overscore（CS）}来定义低电平逻辑信号。 控制逻辑选择性地切换高电平逻辑信号电压（例如，V +电源电压）或低电平逻辑信号电压（{overscore（CS）}）以产生输出数字逻辑信号。 在本发明的另一个实施例中，分离的逻辑电平信号INH和INL可以被控制逻辑选择性地切换以产生独立于电源电压V +和V-的输出逻辑电平信号。
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