摘要:
A semiconductor memory device includes a memory cell array a redundant enable signal generating circuit and redundant decoder. The memory cell array includes memory cell array blocks including column selecting signal lines and lower and upper blocks. The redundant enable signal generating circuit programming defective addresses, during a mode setting operation and generating a redundant enable signal when the defective addresses are applied during an operation. The redundant decoder including decoders selecting a corresponding redundant column selecting signal line in response to the redundant enable signal, a corresponding block address, and a lower and upper block address, wherein each of the of decoders is electrically connected to one of the lower and upper blocks.
摘要:
A semiconductor memory device includes a memory cell array a redundant enable signal generating circuit and redundant decoder. The memory cell array includes memory cell array blocks including column selecting signal lines and lower and upper blocks. The redundant enable signal generating circuit programming defective addresses, during a mode setting operation and generating a redundant enable signal when the defective addresses are applied during an operation. The redundant decoder including decoders selecting a corresponding redundant column selecting signal line in response to the redundant enable signal, a corresponding block address, and a lower and upper block address, wherein each of the of decoders is electrically connected to one of the lower and upper blocks.
摘要:
In an embodiment, a semiconductor memory device has a small number of repair signal transmission lines. The semiconductor memory device includes m repair redundancy blocks, each including n repair redundant word lines, and m and n being natural numbers; and a control circuit generating n repair information signals to select the n repair redundant word lines and m block selection information signals to select the m repair redundancy blocks, and transmitting the n repair information signals and the m block selection information signals to the m repair redundancy blocks. The n repair information signals are shared by the m repair redundancy blocks. The control circuit includes n×m unit fuse boxes, n unit fuse boxes of which corresponding to each of the m repair redundancy blocks.
摘要:
A signal amplification circuit for a semiconductor memory device includes a current sense amplifier configured to receive a first signal pair and generate a second signal pair on a first pair of lines, an equalizer configured to equalize the first pair of lines, and a latch amplifier configured to generate a latch data output on a second pair of lines in response to the second signal pair.
摘要:
A method of configuring a memory cell array block includes dividing a first unit logic block into sub-array blocks and assigning a portion of the sub-array blocks to a second unit logic block, wherein the memory cell array block corresponds to the portion of the sub-array blocks and the second unit logic block, and the portion of the sub-array blocks and the second unit logic block share a peripheral circuit. The first unit logic block may be divided into the sub-array blocks based on a unit of a word line and/or a unit of a bit line. The peripheral circuit may include a row decoder, a column decoder, a sense amplifier and/or an equalize/precharge circuit. A related addressing method, a memory cell array block and semiconductor memory device are also provided.
摘要:
In an embodiment, a semiconductor memory device has a small number of repair signal transmission lines. The semiconductor memory device includes m repair redundancy blocks, each including n repair redundant word lines, and m and n being natural numbers; and a control circuit generating n repair information signals to select the n repair redundant word lines and m block selection information signals to select the m repair redundancy blocks, and transmitting the n repair information signals and the m block selection information signals to the m repair redundancy blocks. The n repair information signals are shared by the m repair redundancy blocks. The control circuit includes n×m unit fuse boxes, n unit fuse boxes of which corresponding to each of the m repair redundancy blocks.
摘要:
A circuit for controlling timing skew in a semiconductor memory device includes a skew control circuit that is configured generate separate skew control signals for each respective one of a plurality of memory banks included in the semiconductor memory device. Related methods are also disclosed.
摘要:
A method of configuring a memory cell array block includes dividing a first unit logic block into sub-array blocks and assigning a portion of the sub-array blocks to a second unit logic block, wherein the memory cell array block corresponds to the portion of the sub-array blocks and the second unit logic block, and the portion of the sub-array blocks and the second unit logic block share a peripheral circuit. The first unit logic block may be divided into the sub-array blocks based on a unit of a word line and/or a unit of a bit line. The peripheral circuit may include a row decoder, a column decoder, a sense amplifier and/or an equalize/precharge circuit. A related addressing method, a memory cell array block and semiconductor memory device are also provided.