公开(公告)号：US20080040697A1

公开(公告)日：2008-02-14

申请号：US11875986

申请日：2007-10-22

申请人： Dureseti Chidambarrao ,  Ricardo Donaton ,  Jack Mandelman

发明人： Dureseti Chidambarrao ,  Ricardo Donaton ,  Jack Mandelman

IPC分类号： G06F17/50

CPC分类号： H01L29/4983 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

摘要： Device structure embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a gate electrode of a device, such as a field effect transistor, having an air gap or void disposed adjacent to a sidewall of the gate electrode. The void may be bounded by a dielectric spacer proximate to the sidewall of the gate electrode and a dielectric layer having a spaced relationship with the dielectric spacer.

摘要翻译： 用于设计，制造或测试设计的机器可读介质中的设备结构。 该设计结构包括诸如场效应晶体管的器件的栅电极，其具有邻近栅电极的侧壁设置的气隙或空隙。 空隙可以由靠近栅电极的侧壁的电介质隔离物和与电介质间隔物具有间隔关系的电介质层界定。

公开(公告)号：US20070257249A1

公开(公告)日：2007-11-08

申请号：US11381810

申请日：2006-05-05

申请人： Anda Mocuta ,  Dureseti Chidambarrao ,  Ricardo Donaton ,  David Onsongo ,  Kern Rim

发明人： Anda Mocuta ,  Dureseti Chidambarrao ,  Ricardo Donaton ,  David Onsongo ,  Kern Rim

IPC分类号： H01L31/00

CPC分类号： H01L21/823807 ,  H01L29/1054 ,  H01L29/66636 ,  H01L29/78687

摘要： A semiconductor structure and method of manufacturing a semiconductor device, and more particularly, an NFET device. The devices includes a stress receiving layer provided over a stress inducing layer with a material at an interface there between which reduces the occurrence and propagation of misfit dislocations in the structure. The stress receiving layer is silicon (Si), the stress inducing layer is silicon-germanium (SiGe) and the material is carbon which is provided by doping the layers during formation of the device. The carbon can be doped throughout the whole of the SiGe layer also.

摘要翻译： 一种制造半导体器件的半导体结构和方法，特别是NFET器件。 这些装置包括在应力诱导层上提供的应力接收层，其中在其间的界面处的材料减少了结构中失配位错的发生和传播。 应力接收层是硅（Si），应力诱导层是硅锗（SiGe），并且材料是在形成器件期间通过掺杂层提供的碳。 也可以在整个SiGe层中掺杂碳。

公开(公告)号：US20070254423A1

公开(公告)日：2007-11-01

申请号：US11380689

申请日：2006-04-28

申请人： Dureseti Chidambarrao ,  Ricardo Donaton ,  William Henson ,  Kern Rim

发明人： Dureseti Chidambarrao ,  Ricardo Donaton ,  William Henson ,  Kern Rim

IPC分类号： H01L21/8234 ,  H01L21/336

CPC分类号： H01L21/823814 ,  H01L21/823807 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848 ,  Y10S438/938

摘要： The invention relates to a semiconductor structure and method of manufacturing and more particularly to a CMOS device with a stress inducing material embedded in both gates and also in the source/drain region of the PFET and varying thickness of the PFET and NFET channel. In one embodiment, the structure enhances the device performance by varying the thickness of the top Silicon layer respective to the NFET or the PFET.

摘要翻译： 本发明涉及半导体结构和制造方法，更具体地说涉及一种CMOS器件，其具有嵌入在PFET的栅极和源极/漏极区域中以及PFET和NFET沟道的变化厚度的应力诱导材料。 在一个实施例中，该结构通过改变相应于NFET或PFET的顶部硅层的厚度来增强器件性能。

公开(公告)号：US20070254422A1

公开(公告)日：2007-11-01

申请号：US11380688

申请日：2006-04-28

申请人： Dureseti Chidambarrao ,  Ricardo Donaton ,  William Henson ,  Kern Rim

发明人： Dureseti Chidambarrao ,  Ricardo Donaton ,  William Henson ,  Kern Rim

IPC分类号： H01L21/8234 ,  H01L21/336

CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1054 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848 ,  Y10S438/938

摘要： A semiconductor structure and method of manufacturing and more particularly a CMOS device with a stress inducing material embedded in both gates and also in the source/drain region of the PFET. The PFET region and the NFET region having a different sized gate to vary the device performance of the NFET and the PFET.

摘要翻译： 一种半导体结构和制造方法，更具体地说是具有嵌入在PFET的栅极和源极/漏极区域中的应力诱导材料的CMOS器件。 PFET区域和NFET区域具有不同尺寸的栅极，以改变NFET和PFET的器件性能。

公开(公告)号：US20070069300A1

公开(公告)日：2007-03-29

申请号：US11162959

申请日：2005-09-29

申请人： Kangguo Cheng ,  Dureseti Chidambarrao ,  Brian Greene ,  Jack Mandelman ,  Kern Rim

发明人： Kangguo Cheng ,  Dureseti Chidambarrao ,  Brian Greene ,  Jack Mandelman ,  Kern Rim

IPC分类号： H01L29/94

CPC分类号： H01L21/2652 ,  H01L21/02203 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02299 ,  H01L21/31662 ,  H01L29/1083 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

摘要： A MOSFET structure includes a planar semiconductor substrate, a gate dielectric and a gate. An ultra-thin (UT) semiconductor-on-insulator channel extends to a first depth below the top surface of the substrate and is self-aligned to and is laterally coextensive with the gate. Source-drain regions, extend to a second depth greater than the first depth below the top surface, and are self-aligned to the UT channel region. A first BOX region extends across the entire structure, and vertically from the second depth to a third depth below the top surface. An upper portion of a second BOX region under the UT channel region is self-aligned to and is laterally coextensive with the gate, and extends vertically from the first depth to a third depth below the top surface, and where the third depth is greater than the second depth.

摘要翻译： MOSFET结构包括平面半导体衬底，栅极电介质和栅极。 超薄（UT）绝缘体上半导体通道延伸到衬底的顶表面下方的第一深度，并且与栅极自对准并且横向共延伸。 源极 - 漏极区域延伸到大于顶部表面下方的第一深度的第二深度，并且与UT沟道区域自对准。 第一BOX区域跨越整个结构延伸，并且从第二深度垂直延伸到顶表面下方的第三深度。 在UT通道区域下面的第二BOX区域的上部自对准并且与栅极横向共同延伸，并且从第一深度垂直延伸到顶表面下方的第三深度，并且其中第三深度大于 第二个深度。

公开(公告)号：US20060057787A1

公开(公告)日：2006-03-16

申请号：US10536483

申请日：2002-11-25

申请人： Bruce Doris ,  Dureseti Chidambarrao ,  Meikei Leong ,  Jack Mandelman

发明人： Bruce Doris ,  Dureseti Chidambarrao ,  Meikei Leong ,  Jack Mandelman

IPC分类号： H01L21/84 ,  H01L27/12

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L29/7843 ,  H01L29/785

摘要： A semiconductor device structure, includes a PMOS device 200 and an NMOS device 300 disposed on a substrate 1,2, the PMOS device including a compressive layer 6 stressing an active region of the PMOS device, the NMOS device including a tensile layer 9 stressing an active region of the NMOS device, wherein the compressive layer includes a first dielectric material, the tensile layer includes a second dielectric material, and the PMOS and NMOS devices are FinFET devices 200, 300.

摘要翻译： 半导体器件结构包括PMOS器件200和设置在衬底1,2上的NMOS器件300，PMOS器件包括压迫PMOS器件的有源区的压缩层6，NMOS器件包括拉伸层9， 所述NMOS器件的有源区，其中所述压缩层包括第一介电材料，所述拉伸层包括第二介电材料，并且所述PMOS和NMOS器件为FinFET器件200,300。

公开(公告)号：US20050280051A1

公开(公告)日：2005-12-22

申请号：US11200958

申请日：2005-08-10

申请人： Dureseti Chidambarrao ,  Omer Dokumaci ,  Bruce Doris ,  Jack Mandelman

发明人： Dureseti Chidambarrao ,  Omer Dokumaci ,  Bruce Doris ,  Jack Mandelman

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/80 ,  H01L31/109 ,  H01L31/112

CPC分类号： H01L29/7846 ,  H01L21/76232 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/785

摘要： A substrate under tension and/or compression improves performance of devices fabricated therein. Tension and/or compression can be imposed on a substrate through selection of appropriate STI fill material. The STI regions are formed in the substrate layer and impose forces on adjacent substrate areas. The substrate areas under compression or tension exhibit charge mobility characteristics different from those of a non-stressed substrate. By controllably varying these stresses within NFET and PFET devices formed on a substrate, improvements in IC performance are achieved.

公开(公告)号：US20050040460A1

公开(公告)日：2005-02-24

申请号：US10935136

申请日：2004-09-07

申请人： Dureseti Chidambarrao ,  Omer Dokumaci ,  Bruce Doris ,  Jack Mandelman ,  Xavier Baie

发明人： Dureseti Chidambarrao ,  Omer Dokumaci ,  Bruce Doris ,  Jack Mandelman ,  Xavier Baie

IPC分类号： H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/423 ,  H01L29/808 ,  H03B1/00 ,  H01L29/76 ,  H03K3/00

CPC分类号： H01L29/6656 ,  H01L21/823807 ,  H01L21/823864 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42316 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/808

摘要： A substrate under tension and/or compression improves performance of devices fabricated therein. Tension and/or compression can be imposed on a substrate through selection of appropriate gate sidewall spacer material disposed above a device channel region wherein the spacers are formed adjacent both the gate and the substrate and impose forces on adjacent substrate areas. Another embodiment comprises compressive stresses imposed in the plane of the channel using SOI sidewall spacers made of polysilicon that is expanded by oxidation. The substrate areas under compression or tension exhibit charge mobility characteristics different from those of a non-stressed substrate. By controllably varying these stresses within NFET and PFET devices formed on a substrate, improvements in IC performance have been demonstrated.

摘要翻译： 在张力和/或压缩下的基底改善了在其中制造的器件的性能。 可以通过选择设置在器件沟道区域上方的适当的栅极侧壁间隔物施加张力和/或压缩，其中间隔物邻近栅极和衬底形成，并且在邻近衬底区域上施加力。 另一个实施例包括使用通过氧化扩展的多晶硅制成的SOI侧壁间隔施加在沟道的平面中的压应力。 在压缩或张力下的衬底区域表现出不同于非应力衬底的电荷迁移率特性。 通过可控地改变在衬底上形成的NFET和PFET器件内的这些应力，已经证明了IC性能的提高。

公开(公告)号：US06724031B1

公开(公告)日：2004-04-20

申请号：US10340999

申请日：2003-01-13

申请人： Hiroyuki Akatsu ,  Dureseti Chidambarrao ,  Ramachandra Divakaruni ,  Jack Mandelman ,  Carl J. Radens

发明人： Hiroyuki Akatsu ,  Dureseti Chidambarrao ,  Ramachandra Divakaruni ,  Jack Mandelman ,  Carl J. Radens

IPC分类号： H01L27108

CPC分类号： H01L27/10864 ,  H01L27/10841 ,  H01L27/10867 ,  H01L29/945

摘要： A dynamic random access memory cell comprising: a trench capacitor formed in a silicon substrate; a vertical MOSFET formed in a silicon substrate above the trench capacitor, the vertical MOSFET having a gate electrode, a first source/drain region extending from a surface of the silicon substrate into the silicon substrate, a buried second source/drain region electrically contacting the trench capacitor, a channel region formed in the silicon substrate between the first source/drain region and the buried second source/drain region and a gate oxide layer disposed between the gate electrode and the channel region; the first source/drain region also belonging to an adjacent vertical MOSFET, the adjacent vertical MOSFET having a buried third source/drain region electrically connected to an adjacent trench capacitor, the buried second and third source/drain regions extending toward one another; and a punch through prevention region disposed between the buried second and third source/drain regions.

摘要翻译： 一种动态随机存取存储单元，包括：形成在硅衬底中的沟槽电容器; 在所述沟槽电容器上方的硅衬底中形成的垂直MOSFET，所述垂直MOSFET具有栅极电极，从所述硅衬底的表面延伸到所述硅衬底的第一源极/漏极区域，与所述第二源极/漏极区域电接触的第二源极/ 沟槽电容器，形成在第一源极/漏极区域和埋入的第二源极/漏极区域之间的硅衬底中的沟道区域和设置在栅极电极和沟道区域之间的栅极氧化物层; 第一源极/漏极区域也属于相邻的垂直MOSFET，相邻的垂直MOSFET具有电连接到相邻沟槽电容器的掩埋的第三源极/漏极区域，所述埋入的第二和第三源极/漏极区域彼此延伸; 以及设置在埋入的第二和第三源极/漏极区之间的穿通防止区域。

公开(公告)号：US09059316B2

公开(公告)日：2015-06-16

申请号：US13397860

申请日：2012-02-16

申请人： Yaocheng Liu ,  Dureseti Chidambarrao ,  Oleg Gluschenkov ,  Judson R. Holt ,  Renee T. Mo ,  Kern Rim

发明人： Yaocheng Liu ,  Dureseti Chidambarrao ,  Oleg Gluschenkov ,  Judson R. Holt ,  Renee T. Mo ,  Kern Rim

IPC分类号： H01L21/8238 ,  H01L21/768 ,  H01L21/84 ,  H01L27/12 ,  H01L29/66 ,  H01L29/78 ,  H01L27/32 ,  H01L29/165

CPC分类号： H01L21/823864 ,  H01L21/76886 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/3279 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： While embedded silicon germanium alloy and silicon carbon alloy provide many useful applications, especially for enhancing the mobility of MOSFETs through stress engineering, formation of alloyed silicide on these surfaces degrades device performance. The present invention provides structures and methods for providing unalloyed silicide on such silicon alloy surfaces placed on semiconductor substrates. This enables the formation of low resistance contacts for both mobility enhanced PFETs with embedded SiGe and mobility enhanced NFETs with embedded Si:C on the same semiconductor substrate. Furthermore, this invention provides methods for thick epitaxial silicon alloy, especially thick epitaxial Si:C alloy, above the level of the gate dielectric to increase the stress on the channel on the transistor devices.

摘要翻译： 虽然嵌入式硅锗合金和硅碳合金提供了许多有用的应用，特别是为了通过应力工程增强MOSFET的迁移率，在这些表面上形成合金化硅化物降低了器件性能。 本发明提供了在放置在半导体衬底上的这种硅合金表面上提供非合金硅化物的结构和方法。 这使得能够在具有嵌入式SiGe的迁移率增强的PFET和在同一半导体衬底上具有嵌入的Si：C的迁移率增强的NFET形成低电阻触点。 此外，本发明提供了在栅极电介质的电平之上的厚外延硅合金，特别是厚的外延Si：C合金的方法，以增加晶体管器件上的沟道上的应力。