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公开(公告)号：US12095477B2
公开(公告)日：2024-09-17
申请号：US18364421
申请日：2023-08-02
Inventor： Sung-Ik Park , Sun-Hyoung Kwon , Jae-Young Lee , Heung-Mook Kim , Nam-Ho Hur
CPC classification number: H03M13/1165 , H03M13/1105 , H03M13/255 , H03M13/2792 , H03M13/616 , H03M13/6552 , H04L1/0041 , H04L1/0042 , H04L1/0071 , H04L27/3422 , H04L1/0057
Abstract: A modulator and a modulation method using a non-uniform 16-symbol signal constellation are disclosed. The modulator includes a memory and a processor. The memory receives a codeword corresponding to a low-density parity check (LDPC) code having a code rate of 4/15. The processor maps the codeword to 16 symbols of the non-uniform 16-symbol signal constellation on a 4-bit basis.
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公开(公告)号：US12095475B2
公开(公告)日：2024-09-17
申请号：US18338081
申请日：2023-06-20
Inventor： Sung-Ik Park , Sun-Hyoung Kwon , Jae-Young Lee , Heung-Mook Kim
CPC classification number: H03M13/1148 , H03M13/1105 , H03M13/1165 , H03M13/255 , H03M13/27 , H03M13/2778 , H03M13/2906 , H03M13/618 , H03M13/6362 , G06T7/162 , H03M13/1102 , H03M13/1111 , H03M13/152 , H04W72/0466
Abstract: A zero padding apparatus and method for fixed length signaling information are disclosed. A zero padding apparatus according to an embodiment of the present invention includes a processor configured to generate a LDPC information bit string by deciding a number of groups whose all bits are to be filled with 0 using a difference between a length of the LDPC information bit string and a length of a BCH-encoded bit string, selecting the groups using a shortening pattern order to fill all the bits of the groups with 0, and filling at least a part of remaining groups, which are not filled with 0, with the BCH-encoded bit string; and memory configured to provide the LDPC information bit string to an LDPC encoder.
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公开(公告)号：US11916572B2
公开(公告)日：2024-02-27
申请号：US17864144
申请日：2022-07-13
Inventor： Sung-Ik Park , Heung-Mook Kim , Sun-Hyoung Kwon , Nam-Ho Hur
CPC classification number: H03M13/1157 , H03M13/1165 , H03M13/1177 , H03M13/616 , H03M13/618
Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 7/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
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4.发明授权公开(公告)号：US11778076B2
公开(公告)日：2023-10-03
申请号：US17882848
申请日：2022-08-08
Inventor： Jae-Young Lee , Heung-Mook Kim , Sung-Ik Park , Sun-Hyoung Kwon
IPC: H04L69/324 , H04L5/00 , H04L1/00 , H04L69/323 , H04H60/07
CPC classification number: H04L69/324 , H04L1/005 , H04L1/007 , H04L1/0041 , H04L1/0057 , H04L1/0058 , H04L1/0071 , H04L5/0044 , H04L69/323 , H04H60/07 , H04L5/0007 , Y02D30/70
Abstract: An apparatus and method for broadcast signal frame using layered division multiplexing are disclosed. An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a combiner configured to generate a multiplexed signal by combining a core layer signal and an enhanced layer signal at different power levels; a power normalizer configured to reduce the power of the multiplexed signal to a power level corresponding to the core layer signal; a time interleaver configured to generate a time-interleaved signal by performing interleaving that is applied to both the core layer signal and the enhanced layer signal; and a frame builder configured to generate a broadcast signal frame including a preamble for signaling time interleaver information shared by the core layer signal and the enhanced layer signal, using the time-interleaved signal.
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公开(公告)号：US11700016B2
公开(公告)日：2023-07-11
申请号：US17694774
申请日：2022-03-15
Inventor： Sung-Ik Park , Sun-Hyoung Kwon , Jae-Young Lee , Heung-Mook Kim
CPC classification number: H03M13/1102 , H03M13/116 , H03M13/2778 , H03M13/2903 , H03M13/618 , H03M13/152 , H03M13/253 , H03M13/255 , H03M13/2906
Abstract: A zero padding apparatus and method for variable length signaling information are disclosed. A zero padding apparatus according to an embodiment of the present invention includes a processor configured to generate a LDPC information bit string by deciding a number of groups whose all bits are to be filled with 0 using a difference between a length of the LDPC information bit string and a length of a BCH-encoded bit string, selecting the groups using a shortening pattern order to fill all the bits of the groups with 0, and filling at least a part of remaining groups, which are not filled with 0, with the BCH-encoded bit string; and memory configured to provide the LDPC information bit string to an LDPC encoder.
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Patent Agency Ranking
6.发明公开公开(公告)号：US20230188255A1
公开(公告)日：2023-06-15
申请号：US18165876
申请日：2023-02-07
Inventor： Sung-Ik PARK , Jae-Young Lee , Sun-Hyoung Kwon , Nam-Ho Hur , Heung-Mook Kim
CPC classification number: H04L1/0041 , H04L1/0057 , H04L5/0014 , H04L5/0075 , H04L1/0071 , H04J99/00 , H04L27/2626
Abstract: An apparatus and method for transmitting broadcast signal to which channel bonding is applied are disclosed. The apparatus according to the present invention includes an input formatting unit configured to generate baseband packets corresponding to a plurality of packet types using data corresponding to a physical layer pipe; a stream partitioner configured to partition the baseband packets into a plurality of partitioned streams corresponding to the plurality of packet types; BICM units configured to perform error correction encoding, interleaving and modulation corresponding to the plurality of partitioned streams, respectively; and waveform generators configured to generate RF transmission signals corresponding to the plurality of partitioned streams, respectively.
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公开(公告)号：US11665510B2
公开(公告)日：2023-05-30
申请号：US17242126
申请日：2021-04-27
Inventor： Jae-Young Lee , Sung-Ik Park , Bo-Mi Lim , Sun-Hyoung Kwon , Heung-Mook Kim
CPC classification number: H04W4/06 , H04J11/00 , H04L1/0071 , H04L1/0083 , H04L5/0044 , H04L12/184 , H04L27/26 , H04L27/2602 , H04L27/2605 , H04L27/2613 , H04W52/346 , H04J2011/0013 , H04L1/0058 , H04L27/26136 , H04L2001/0093 , Y02D30/70
Abstract: An apparatus and method for broadcast signal frame using layered division multiplexing are disclosed. An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a combiner configured to generate a multiplexed signal by combining a core layer signal and an enhanced layer signal at different power levels; a power normalizer configured to reduce the power of the multiplexed signal to a power level corresponding to the core layer signal; a time interleaver configured to generate a time-interleaved signal by performing interleaving that is applied to both the core layer signal and the enhanced layer signal; and a frame builder configured to generate a broadcast signal frame including a preamble for signaling, start position information of Physical Layer Pipes (PLPs) and time interleaver information shared by the core layer signal and the enhanced layer signal.
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公开(公告)号：US11564190B2
公开(公告)日：2023-01-24
申请号：US17735261
申请日：2022-05-03
Inventor： Jae-Young Lee , Sung-Ik Park , Sun-Hyoung Kwon , Heung-Mook Kim , Nam-Ho Hur
Abstract: Disclosed herein are a gateway-signaling method for frequency/timing offsets and an apparatus for the same. An apparatus for transmitting a broadcast signal according to an embodiment of the present invention includes a frequency/timing decision unit for determining a center frequency to which a frequency offset is applied using a carrier offset, which is identified using a timing and a management packet transmitted through a Studio-to-Transmitter Link (STL); and an RF signal generation unit for generating an RF signal to be transmitted, which corresponds to the center frequency.
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公开(公告)号：US11381256B2
公开(公告)日：2022-07-05
申请号：US17021328
申请日：2020-09-15
Inventor： Sung-Ik Park , Sun-Hyoung Kwon , Jae-Young Lee , Heung-Mook Kim
Abstract: A parity interleaving apparatus and method for variable length signaling information are disclosed. A parity interleaving apparatus according to an embodiment of the present invention includes a processor configured to generate a parity bit string for parity puncturing by segmenting parity bits of an LDPC codeword whose length is 16200 and whose code rate is 3/15, into a plurality of groups, and group-wise interleaving the groups using an order of group-wise interleaving; and memory configured to provide the parity bit string for parity puncturing to a parity puncturing unit.
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公开(公告)号：US11316536B2
公开(公告)日：2022-04-26
申请号：US16808284
申请日：2020-03-03
Inventor： Sung-Ik Park , Heung-Mook Kim , Sun-Hyoung Kwon , Nam-Ho Hur
Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 4/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
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