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    Circuits and techniques for conditioning differential signals
    5.
    发明授权
    Circuits and techniques for conditioning differential signals 失效
    差分信号调理电路和技术

    公开(公告)号：US06985021B1

    公开(公告)日：2006-01-10

    申请号：US10652521

    申请日：2003-08-29

    申请人： Arch Zaliznyak ,  William Bereza ,  Henry Lui ,  Chong Lee ,  Rakesh Patel

    发明人： Arch Zaliznyak ,  William Bereza ,  Henry Lui ,  Chong Lee ,  Rakesh Patel

    IPC分类号： H03F3/45

    CPC分类号： H03F3/45475 ,  H03F3/4521 ,  H03F3/45928 ,  H03F2200/513 ,  H03F2203/45088 ,  H03F2203/45101 ,  H03F2203/45136 ,  H03F2203/45236 ,  H03F2203/45366 ,  H03F2203/45544 ,  H03F2203/45561 ,  H03F2203/45586 ,  H03F2203/45592 ,  H03F2203/45594 ,  H03F2203/45616 ,  H03K19/003

    摘要： Circuitry is provided that conditions a differential input signal such that when the signal is received by a multi-standard differential input buffer, the buffer is able to process the conditioned signal without pronounced increases in propagation delay, thereby keeping signal jitter to a minimum. The circuitry further enables input buffers to operate according to desired operating parameters even when the supply voltage powering the input buffer is relatively low. The circuitry operates by shifting the common-mode voltage to a range that puts the input buffer in a favorable common-mode voltage range of operation. The circuitry may be coupled with a programmably controlled amplifier that amplifies the amplitude of the conditioned differential signal prior to being received by the input buffer. Amplifying the signal prevents problems typically associated with data-dependent jitter and intersymbol interference by boosting the voltage amplitude to a level that is readily processed by the input buffer.

    摘要翻译： 提供电路，其规定差分输入信号，使得当信号被多标准差分输入缓冲器接收时，缓冲器能够处理调节后的信号而传播延迟不会明显增加，从而将信号抖动保持在最小。 该电路还使输入缓冲器能够根据期望的操作参数进行操作，即使为输入缓冲器供电的电源电压相对较低。 电路通过将共模电压移动到使输入缓冲器处于有利的共模电压操作范围的范围来工作。 电路可以与可编程控制的放大器耦合，放大器在由输入缓冲器接收之前放大经调节的差分信号的幅度。 通过将电压幅度升高到输入缓冲器容易处理的电平，放大信号可防止通常与数据相关的抖动和符号间干扰相关的问题。

    ENHANCED PASSGATE STRUCTURES FOR REDUCING LEAKAGE CURRENT
    6.
    发明申请
    ENHANCED PASSGATE STRUCTURES FOR REDUCING LEAKAGE CURRENT 有权
    用于降低泄漏电流的增强通孔结构

    公开(公告)号：US20060028240A1

    公开(公告)日：2006-02-09

    申请号：US10910891

    申请日：2004-08-03

    申请人： Henry Lui ,  Malik Kabani ,  Rakesh Patel ,  Tim Hoang

    发明人： Henry Lui ,  Malik Kabani ,  Rakesh Patel ,  Tim Hoang

    IPC分类号： H03K19/173

    CPC分类号： H03K19/1778 ,  H03K19/17784 ,  H03K19/17792

    摘要： Enhanced passgate structures for use in low-voltage systems are presented in which the operational speed of the passgate structures is maximized, while minimizing leakage current when the structure is turned “OFF.” In one arrangement, the VT of the pass-gate structures is increased relative to the VT of other transistors fabricated according to a particular process dimension. In addition, a passgate activation voltage is applied to the passgate structures such that the passgate activation voltage is higher in voltage than a nominal voltage being supplied to circuitry other than the passgate structures.

    摘要翻译： 提出了在低压系统中使用的增强型门控结构，其中通道结构的操作速度最大化，同时使结构“OFF”时的漏电流最小化。 在一种布置中，栅极结构的栅极相对于根据特定工艺尺寸制造的其它晶体管的V IN T T T T增加。 此外，通道激活电压被施加到通道结构，使得通电门激活电压的电压高于提供给非门电路结构以外的电路的标称电压。

    Apparatus and method for reset distribution
    7.
    发明授权
    Apparatus and method for reset distribution 有权
    复位分配的装置和方法

    公开(公告)号：US07343569B1

    公开(公告)日：2008-03-11

    申请号：US11351425

    申请日：2006-02-10

    申请人： John Lam ,  Arch Zaliznyak ,  Chong Lee ,  Rakesh Patel ,  Vinson Chan

    发明人： John Lam ,  Arch Zaliznyak ,  Chong Lee ,  Rakesh Patel ,  Vinson Chan

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5054 ,  G06F2217/66

    摘要： A skew-tolerant, glitch-free reset distribution apparatus and method are provided in an intellectual property (IP) block that supports a multi-channel input/output protocol. During reset mode, synchronizers are used to create more predictable timing, to pipeline the propagation delay, and to tolerate RC-induced skews of up to a clock period in routing a reset signal to all the channels and within the channels in an IP block. Two control signals, which are available from programmable logic resource core circuitry, are used to control the input of the reset signal into the IP block. Because the control signals are designed to be glitch-free, the reset signal is therefore also glitch-free, thus preventing the IP block from inadvertently transitioning into or out of reset mode.

    摘要翻译： 在支持多通道输入/输出协议的知识产权（IP）块中提供了容错，无毛刺的复位分配装置和方法。 在复位模式期间，使用同步器创建更可预测的时序，流水线传播延迟，并允许在将复位信号路由到IP模块中的所有通道和通道内的RC时钟周期的RC引起的偏差。 两个控制信号可从可编程逻辑资源核心电路获得，用于控制复位信号输入到IP模块。 由于控制信号被设计为无毛刺，因此复位信号也无毛刺，从而防止IP块无意中转换或复位。

    Multiple data rates in programmable logic device serial interface
    8.
    发明申请
    Multiple data rates in programmable logic device serial interface 有权
    可编程逻辑器件串行接口中的多个数据速率

    公开(公告)号：US20070011370A1

    公开(公告)日：2007-01-11

    申请号：US11177007

    申请日：2005-07-08

    申请人： Ramanand Venkata ,  Rakesh Patel ,  Chong Lee

    发明人： Ramanand Venkata ,  Rakesh Patel ,  Chong Lee

    IPC分类号： G06F13/38

    CPC分类号： H03K19/17744

    摘要： A serial interface for a programmable logic device supports a wide range of data rates by providing a first number of channels supporting a first range of data rates and a second number of channels supporting a second range of data rates. The first range of data rates is preferably lower than the second range of data rates and preferably the first number of channels is higher than the second number of channels which preferably is 1. For backward compatibility with existing devices, the first number of channels in each interface preferably is four. Each channel preferably includes a physical medium attachment module and a physical coding sublayer module. Each of the higher-speed channels in the second number of channels preferably also includes a clock management unit, while the lower-speed channels in the first number of channels preferably share one or more clock management units.

    摘要翻译： 用于可编程逻辑器件的串行接口通过提供支持第一范围的数据速率的第一数量的通道和支持第二数据速率范围的第二数量的通道来支持宽范围的数据速率。 数据速率的第一范围优选地低于数据速率的第二范围，并且优选地，第一数量的信道高于优选为1的信道的第二数量。为了与现有设备的向后兼容，每个信道中的第一数量的信道 界面最好是四。 每个通道优选地包括物理介质连接模块和物理编码子层模块。 第二数量的频道中的每一个较高频道优选地还包括时钟管理单元，而第一数量的频道中的较低速频道优选地共享一个或多个时钟管理单元。

    Next generation 8B10B architecture
    10.
    发明申请
    Next generation 8B10B architecture 有权

    公开(公告)号：US20070139232A1

    公开(公告)日：2007-06-21

    申请号：US11655797

    申请日：2007-01-18

    申请人： Ramanand Venkata ,  Rakesh Patel ,  Chong Lee

    发明人： Ramanand Venkata ,  Rakesh Patel ,  Chong Lee

    IPC分类号： H03M7/00

    CPC分类号： G06F13/385

    摘要： Eight-bit ten-bit (8B10B) coding is provided in a hard intellectual property (IP) block with the capability of supporting a greater range of data rates (e.g., data rates less than, equal to, and greater than 3.125 Gbps). Each channel of high speed serial interface circuitry includes receiver circuitry having two 8B10B decoders and transmitter circuitry having two 8B10B encoders. The receiver and transmitter circuitry can be configured to operate in one of three modes of operation: cascade mode, dual channel mode, and single channel mode.