公开(公告)号：US20080020546A1

公开(公告)日：2008-01-24

申请号：US11862706

申请日：2007-09-27

申请人： Edward COONEY ,  Vincent McGahay ,  Thomas Shaw ,  Anthony Stamper ,  Matthew Colburn

发明人： Edward COONEY ,  Vincent McGahay ,  Thomas Shaw ,  Anthony Stamper ,  Matthew Colburn

IPC分类号： H01L21/475 ,  H01L21/302 ,  H01L21/32 ,  H01L21/467

CPC分类号： H01L21/76829 ,  H01L21/31144 ,  H01L21/76828 ,  H01L21/78

摘要： The present invention relates to a process for improved interfacial adhesion of dielectrics using patterned roughing. Improved adhesion strength between layers and substrates can be achieved through increasing the roughness of the interface between the materials. Roughness may including any disturbance of an otherwise generally smooth surface, such as grooves, indents, holes, trenches, and/or the like. Roughing on the interface may be achieved by depositing a material on a surface of the substrate to act as a mask and then using an etching process to induce the roughness. The material, acting as a mask, allows etching to occur on a fine, or sub-miniature, scale below the Scale achieved with a conventional photo mask and lithography to achieve the required pattern roughing. Another material is then deposited on the roughened surface of the substrate, filling in the roughing and adhering to the substrate.

摘要翻译： 本发明涉及使用图案化粗糙化改善电介质的界面粘附的方法。 可以通过增加材料之间的界面的粗糙度来实现层和基底之间的改善的粘附强度。 粗糙度可能包括任何干扰通常平滑的表面，如凹槽，凹痕，孔，沟槽等。 可以通过在衬底的表面上沉积材料作为掩模，然后使用蚀刻工艺来引起粗糙度来实现界面上的粗加工。 用作掩模的材料允许蚀刻在以常规光掩模和光刻实现的规模以下的精细或次微小尺度上发生，以实现所需的图案粗糙化。 然后将另一种材料沉积在基底的粗糙表面上，填充粗加工并粘附到基底上。

公开(公告)号：US20050277266A1

公开(公告)日：2005-12-15

申请号：US10710034

申请日：2004-06-14

申请人： Edward Cooney ,  Vincent McGahay ,  Thomas Shaw ,  Anthony Stamper ,  Matthew Colburn

发明人： Edward Cooney ,  Vincent McGahay ,  Thomas Shaw ,  Anthony Stamper ,  Matthew Colburn

IPC分类号： C23C14/00 ,  C23C14/32 ,  H01L21/30 ,  H01L21/302 ,  H01L21/311 ,  H01L21/46 ,  H01L21/461 ,  H01L21/768 ,  H01L21/78

CPC分类号： H01L21/76829 ,  H01L21/31144 ,  H01L21/76828 ,  H01L21/78

摘要： The present invention relates to a process for improved interfacial adhesion of dielectrics using patterned roughing. Improved adhesion strength between layers and substrates can be achieved through increasing the roughness of the interface between the materials. Roughness may including any disturbance of an otherwise generally smooth surface, such as grooves, indents, holes, trenches, and/or the like. Roughing on the interface may be achieved by depositing a material on a surface of the substrate to act as a mask and then using an etching process to induce the roughness. The material, acting as a mask, allows etching to occur on a fine, or sub-miniature, scale below the Scale achieved with a conventional photo mask and lithography to achieve the required pattern roughing. Another material is then deposited on the roughened surface of the substrate, filling in the roughing and adhering to the substrate.

摘要翻译： 本发明涉及使用图案化粗糙化改善电介质的界面粘附的方法。 可以通过增加材料之间的界面的粗糙度来实现层和基底之间的改善的粘附强度。 粗糙度可能包括任何干扰通常平滑的表面，如凹槽，凹痕，孔，沟槽等。 可以通过在衬底的表面上沉积材料作为掩模，然后使用蚀刻工艺来引起粗糙度来实现界面上的粗加工。 用作掩模的材料允许蚀刻在以常规光掩模和光刻实现的规模以下的精细或次微小尺度上发生，以实现所需的图案粗糙化。 然后将另一种材料沉积在基底的粗糙表面上，填充粗加工并粘附到基底上。

公开(公告)号：US20050167838A1

公开(公告)日：2005-08-04

申请号：US10707996

申请日：2004-01-30

申请人： Daniel Edelstein ,  Matthew Colburn ,  Edward Cooney ,  Timothy Dalton ,  John Fitzsimmons ,  Jeffrey Gambino ,  Elbert Huang ,  Michael Lane ,  Vincent McGahay ,  Lee Nicholson ,  Satyanarayana Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas Shaw ,  Andrew Simon ,  Anthony Stamper

发明人： Daniel Edelstein ,  Matthew Colburn ,  Edward Cooney ,  Timothy Dalton ,  John Fitzsimmons ,  Jeffrey Gambino ,  Elbert Huang ,  Michael Lane ,  Vincent McGahay ,  Lee Nicholson ,  Satyanarayana Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas Shaw ,  Andrew Simon ,  Anthony Stamper

IPC分类号： H01L21/033 ,  H01L21/302 ,  H01L21/311 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L23/532 ,  H01L29/40

CPC分类号： B82Y30/00 ,  H01L21/0332 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

摘要： A method for manufacturing a structure includes providing a structure having an insulator layer with at least one interconnect and forming a sub lithographic template mask on the insulator layer. A selective etching step is used for etching the insulator layer through the sub lithographic template mask to form sub lithographic features near the at least one interconnect. A supra lithographic blocking mask may also be utilized. In another aspect, the method includes forming pinch off sections of sub lithographic size formed in a capping layer on the insulator layer. A semiconductor structure includes an insulator layer having at least one interconnect feature and at least one column formed in the insulator layer. A plurality of sub lithographic features formed on a top portion of the insulator layer and communicating with the at least one column is also provided. The plurality of sub lithographic features have a cross section or diameter less than any of the at least one column. A gap may be prohibited from forming on or near scribe lanes and vias

摘要翻译： 一种制造结构的方法包括提供具有至少一个互连的绝缘层的结构，并在绝缘体层上形成次光刻模板掩模。 选择性蚀刻步骤用于通过子光刻模板掩模蚀刻绝缘体层，以在至少一个互连附近形成亚光刻特征。 还可以使用超光刻阻挡掩模。 另一方面，该方法包括形成在绝缘体层上的覆盖层中形成的亚光刻尺寸的夹断部分。 半导体结构包括具有至少一个互连特征的绝缘体层和形成在绝缘体层中的至少一个列。 还提供了形成在绝缘体层的顶部并与至少一个柱连通的多个次级光刻特征。 所述多个亚光刻特征具有小于或小于所述至少一列中的任何一个的横截面或直径。 可能禁止在划线车道和通道上或附近形成间隙

公开(公告)号：US20070275565A1

公开(公告)日：2007-11-29

申请号：US11838942

申请日：2007-08-15

申请人： Edward Cooney ,  Robert Geffken ,  Vincent McGahay ,  William Motsiff ,  Mark Murray ,  Amanda Piper ,  Anthony Stamper ,  David Thomas ,  Elizabeth Webster

发明人： Edward Cooney ,  Robert Geffken ,  Vincent McGahay ,  William Motsiff ,  Mark Murray ,  Amanda Piper ,  Anthony Stamper ,  David Thomas ,  Elizabeth Webster

IPC分类号： H01L21/311

CPC分类号： H01L23/53238 ,  H01L21/31116 ,  H01L21/32136 ,  H01L21/76838 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and structure for semiconductor structure includes a plurality of adjacent wiring levels, conductors within each of the wiring levels, and liners at least partially surrounding each of the conductors. The liners of adjacent wiring levels are made of different materials which have different etching characteristics and are selectively etchable with respect to one another. The liners can be tantalum, tungsten, etc. The liners surround at least three sides of the conductors. Each of the wiring levels has a first insulator layer which has a first dielectric material. The liners and the conductors are positioned within the first dielectric material. A second insulator layer has a second dielectric material over the first insulator layer. The first dielectric material has a lower dielectric constant than the second dielectric material. The first dielectric material can be silicon dioxide, fluorinated silicon dioxide (FSD), microporous glasses, etc. The second dielectric material can be one of nitrides, oxides, tantalum, tungsten, etc.

摘要翻译： 用于半导体结构的方法和结构包括多个相邻布线层，每个布线层内的导体和至少部分地围绕每个导体的衬垫。 相邻布线层的衬垫由具有不同蚀刻特性并且可相对于彼此选择性地蚀刻的不同材料制成。 衬垫可以是钽，钨等。衬里围绕导体的至少三个侧面。 每个布线层具有第一绝缘体层，其具有第一介电材料。 衬垫和导体位于第一介电材料内。 第二绝缘体层在第一绝缘体层上具有第二电介质材料。 第一电介质材料具有比第二电介质材料低的介电常数。 第一介电材料可以是二氧化硅，氟化二氧化硅（FSD），微孔玻璃等。第二介电材料可以是氮化物，氧化物，钽，钨等中的一种。

公开(公告)号：US20050208781A1

公开(公告)日：2005-09-22

申请号：US10708735

申请日：2004-03-22

申请人： John Fitzsimmons ,  Michael Lane ,  Vincent McGahay ,  Thomas Shaw ,  Anthony Stamper

发明人： John Fitzsimmons ,  Michael Lane ,  Vincent McGahay ,  Thomas Shaw ,  Anthony Stamper

IPC分类号： B05D1/02 ,  H01L21/78 ,  H01L23/00

CPC分类号： H01L23/562 ,  H01L21/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming and the integrated circuit device structure formed having vertical interfaces adjacent an existing crack stop around a perimeter of a chip, whereby the vertical interface controls cracks generated during side processing of the device such as dicing, and in service from penetrating the crack stop. The vertical interface is comprised of a material that prevents cracks from damaging the crack stop by deflecting cracks away from penetrating the crack stop, or by absorbing the generated crack energies. Alternatively, the vertical interface may be a material that allows advancing cracks to lose enough energy such that they become incapable of penetrating the crack stop. The present vertical interfaces can be implemented in a number of ways such as, vertical spacers of release material, vertical trenches of release material or vertical channels of the release material.

摘要翻译： 形成方法和集成电路器件结构形成，具有与现有裂纹相邻的垂直接口围绕芯片的周边，由此垂直接口控制器件的侧面处理期间产生的裂纹，例如切割，并且在穿透裂纹停止 。 垂直界面由防止裂纹破坏裂纹的材料组成，通过使裂纹偏离穿透裂缝，或通过吸收所产生的裂纹能量来防止裂纹破裂。 或者，垂直界面可以是允许前进裂纹失去足够的能量使得它们不能穿透裂缝停止的材料。 现有的垂直接口可以以多种方式实现，例如释放材料的垂直间隔物，释放材料的垂直沟槽或释放材料的垂直通道。

公开(公告)号：US20070152332A1

公开(公告)日：2007-07-05

申请号：US11306596

申请日：2006-01-04

申请人： Anil Chinthakindi ,  Douglas Coolbaugh ,  Ebenezer Eshun ,  Vincent McGahay ,  Anthony Stamper ,  Kunal Vaed ,  Richard Volant

发明人： Anil Chinthakindi ,  Douglas Coolbaugh ,  Ebenezer Eshun ,  Vincent McGahay ,  Anthony Stamper ,  Kunal Vaed ,  Richard Volant

IPC分类号： H01L21/44

CPC分类号： H01L21/76838 ,  H01L23/5223 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to integrated circuits that comprise via-level wirings and/or devices. Specifically, an integrate circuit of the present invention comprises a first line level and a second line level spaced apart from each other, with a via level therebetween. The first and second line levels both comprise metal wirings and/or electronic devices. The via level comprises at least one metal via that extends therethrough to electrically connect the first line level with the second line level. Further, the via level comprises at least one via-level metal wiring and/or electronic device.

摘要翻译： 本发明涉及包括通孔级布线和/或器件的集成电路。 具体而言，本发明的集成电路包括彼此间隔开的第一线路电平和第二线路电平，其间具有通路电平。 第一和第二线路级均包括金属布线和/或电子设备。 通孔级包括至少一个穿过其中的金属通孔，以将第一线路电平与第二线路电平电连接。 此外，通孔电平包括至少一个通孔级金属布线和/或电子器件。

公开(公告)号：US20050014369A1

公开(公告)日：2005-01-20

申请号：US10604367

申请日：2003-07-15

申请人： Edward Cooney, III ,  Anthony Stamper

发明人： Edward Cooney, III ,  Anthony Stamper

IPC分类号： H01L21/00 ,  H01L21/302 ,  H01L21/306 ,  H01L21/311 ,  H01L21/461

CPC分类号： H01L21/67069 ,  H01J2237/022 ,  H01L21/02046 ,  H01L21/31138

摘要： A method of reducing foreign material concentrations in an etch chamber having inner chamber walls is described. The method includes the step of etching a work piece in the etch chamber such that reaction products from the work piece having one or more elements form a first layer of reaction products that partially adhere to the inner chamber walls. A species is introduced into the etch chamber that increases the adhesion of the first layer of reaction products to the inner chamber walls.

摘要翻译： 描述了在具有内室壁的蚀刻室中减少异物浓度的方法。 该方法包括在蚀刻室中蚀刻工件的步骤，使得具有一个或多个元件的工件的反应产物形成部分粘附到内室壁上的第一反应产物层。 将一种物质引入到蚀刻室中，这增加了第一层反应产物与内室壁的粘附性。

公开(公告)号：US20080026566A1

公开(公告)日：2008-01-31

申请号：US11847657

申请日：2007-08-30

申请人： Jeffrey Gambino ,  Edward Cooney ,  Anthony Stamper ,  William Motsiff ,  Michael Lane ,  Andrew Simon

发明人： Jeffrey Gambino ,  Edward Cooney ,  Anthony Stamper ,  William Motsiff ,  Michael Lane ,  Andrew Simon

IPC分类号： H01L21/4763

CPC分类号： H01L21/76811 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76813 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76865 ,  H01L21/76877 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods are disclosed for forming dual damascene back-end-of-line (BEOL) interconnect structures using materials for the vias or studs which are different from those used for the line conductors, or using materials for the via liner which are different from those used for the trench liner, or having a via liner thickness different from that of the trench liner. Preferably, a thick refractory metal is used in the vias for improved mechanical strength while using only a thin refractory metal in the trenches to provide low resistance.

摘要翻译： 公开了用于形成双镶嵌后端（BEOL）互连结构的方法，其使用与用于线路导体的那些不同的通孔或螺柱的材料，或者使用不同于所使用的通孔衬垫的材料 用于沟槽衬垫，或者具有不同于沟槽衬套的通孔衬垫厚度。 优选地，在通孔中使用厚的难熔金属以改善机械强度，同时仅在沟槽中使用薄的难熔金属来提供低电阻。

公开(公告)号：US20050245068A1

公开(公告)日：2005-11-03

申请号：US11174985

申请日：2005-07-05

申请人： Jeffrey Gambino ,  Edward Cooney ,  Anthony Stamper ,  William Motsiff ,  Michael Lane ,  Andrew Simon

发明人： Jeffrey Gambino ,  Edward Cooney ,  Anthony Stamper ,  William Motsiff ,  Michael Lane ,  Andrew Simon

IPC分类号： H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76811 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76813 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76865 ,  H01L21/76877 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods are disclosed for forming dual damascene back-end-of-line (BEOL) interconnect structures using materials for the vias or studs which are different from those used for the line conductors, or using materials for the via liner which are different from those used for the trench liner, or having a via liner thickness different from that of the trench liner. Preferably, a thick refractory metal is used in the vias for improved mechanical strength while using only a thin refractory metal in the trenches to provide low resistance.

摘要翻译： 公开了用于形成双镶嵌后端（BEOL）互连结构的方法，其使用与用于线路导体的那些不同的通孔或螺柱的材料，或者使用不同于所使用的通孔衬垫的材料 用于沟槽衬垫，或者具有不同于沟槽衬套的通孔衬垫厚度。 优选地，在通孔中使用厚的难熔金属以改善机械强度，同时仅在沟槽中使用薄的难熔金属来提供低电阻。

公开(公告)号：US07704876B2

公开(公告)日：2010-04-27

申请号：US11847657

申请日：2007-08-30

申请人： Jeffrey Gambino ,  Edward Cooney, III ,  Anthony Stamper ,  William Thomas Motsiff ,  Michael Lane ,  Andrew Simon

发明人： Jeffrey Gambino ,  Edward Cooney, III ,  Anthony Stamper ,  William Thomas Motsiff ,  Michael Lane ,  Andrew Simon

IPC分类号： H01L21/4763

CPC分类号： H01L21/76811 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76813 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76865 ,  H01L21/76877 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods are disclosed for forming dual damascene back-end-of-line (BEOL) interconnect structures using materials for the vias or studs which are different from those used for the line conductors, or using materials for the via liner which are different from those used for the trench liner, or having a via liner thickness different from that of the trench liner. Preferably, a thick refractory metal is used in the vias for improved mechanical strength while using only a thin refractory metal in the trenches to provide low resistance.

摘要翻译： 公开了用于形成双镶嵌后端（BEOL）互连结构的方法，其使用与用于线路导体的那些不同的通孔或螺柱的材料，或者使用不同于所使用的通孔衬垫的材料 用于沟槽衬垫，或者具有不同于沟槽衬套的通孔衬垫厚度。 优选地，在通孔中使用厚的难熔金属以改善机械强度，同时仅在沟槽中使用薄的难熔金属来提供低电阻。