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196 条记录 (耗时 0.036 秒)

    Hybrid aerial image simulation
    5.
    发明授权
    Hybrid aerial image simulation 有权
    混合航空图像模拟

    公开(公告)号：US06171731B2

    公开(公告)日：2001-01-09

    申请号：US09233885

    申请日：1999-01-20

    申请人： Marina G. Medvedeva ,  Ranko Scepanovic ,  Dusan Petranovic

    发明人： Marina G. Medvedeva ,  Ranko Scepanovic ,  Dusan Petranovic

    IPC分类号： G03F900

    CPC分类号： G03F7/705

    摘要： An aerial image produced by a mask having transmissive portions is simulated by dividing the transmissive portions of the mask into primitive elements and obtaining a spatial frequency function corresponding to each of the primitive elements. The spatial frequency functions corresponding to the primitive elements are combined to obtain a transformed mask transmission function, and the transformed mask transmission function is utilized to generate a simulation of the aerial image.

    摘要翻译： 由具有透射部分的掩模产生的空间图像通过将掩模的透射部分分成原始元素并获得对应于每个基元的空间频率函数而被模拟。 对应于原始元素的空间频率函数被组合以获得变换的掩模传输功能，并且利用变换的掩模传输功能来生成空中图像的模拟。

    Resynthesis method for significant delay reduction
    6.
    发明授权
    Resynthesis method for significant delay reduction 失效
    重新延迟降低的再合成方法

    公开(公告)号：US6109201A

    公开(公告)日：2000-08-29

    申请号：US10395

    申请日：1998-01-21

    申请人： Dusan Petranovic ,  Ranko Scepanovic ,  Stanislav V. Aleshin ,  Mikhail Grinchuk ,  Sergei Gashov

    发明人： Dusan Petranovic ,  Ranko Scepanovic ,  Stanislav V. Aleshin ,  Mikhail Grinchuk ,  Sergei Gashov

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505

    摘要： Integrated circuit chips (IC's) require proper placement of many cells (groups of circuit components) and complex routing of wires to connect the cells. Designing of the IC's require meeting real-world constraints one of which is the performance of the IC, or the period of time required by the integrated circuit to produce the output signals from the time the input signals are available. Typically, the performance of an integrated circuit is determined by the slowest path of the signals, called the critical path. The critical path is usually only a small portion of the IC. The present invention discloses a method and apparatus for transforming the circuits comprising the critical path, thereby increasing the performance of the entire IC. The transformation is performed by segmenting, or blocking, the cells which make up the critical path. Then, each block is transformed, or replaced, with a resynthesized circuit to which both the digital 0 and digital 1 values are provided. The critical path is defined by the fact that the delay at each block is accumulated because each block has to wait for the output signal of the preceding block to use as its input signal. After the resynthesis of the blocks, none of the blocks need to wait for the output signal of its preceding block because each of the resynthesized blocks has the output for all possible inputs values (0 and 1). Thus, the signal delay at each block is not accumulated; rather, the only accumulated delay is the delay of the multiplexors used to select the correct output. The result is a dramatically reduced critical path delay.

    摘要翻译： 集成电路芯片（IC）需要适当放置多个单元（电路组件组）和复杂的导线布线来连接单元。 IC的设计需要满足实际的限制，其中之一是IC的性能，或集成电路从输入信号可用时产生输出信号所需的时间段。 通常，集成电路的性能由称为关键路径的信号的最慢路径决定。 关键路径通常只是IC的一小部分。 本发明公开了一种用于变换包括关键路径的电路的方法和装置，从而提高了整个IC的性能。 通过分割或阻塞构成关键路径的单元来执行转换。 然后，用提供数字0和数字1值的再合成电路对每个块进行变换或替换。 关键路径由每个块的延迟积累的事实定义，因为每个块必须等待前一块的输出信号用作其输入信号。 在块的再合成之后，没有一个块需要等待其前一块的输出信号，因为每个再合并块具有用于所有可能的输入值（0和1）的输出。 因此，每个块的信号延迟不被累加; 相反，唯一累积的延迟是用于选择正确输出的多路复用器的延迟。 结果是大大减少了关键路径延迟。

    Timing-driven placement method utilizing novel interconnect delay model
    7.
    发明授权
    Timing-driven placement method utilizing novel interconnect delay model 失效
    利用新型互连延迟模型的定时驱动放置方法

    公开(公告)号：US06901571B1

    公开(公告)日：2005-05-31

    申请号：US09010396

    申请日：1998-01-21

    申请人： Dusan Petranovic ,  Ranko Scepanovic ,  Ivan Pavisic

    发明人： Dusan Petranovic ,  Ranko Scepanovic ,  Ivan Pavisic

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5072

    摘要： A method for optimal placement of cells on a surface of an integrated circuit, comprising the steps of comparing a placement of cells to predetermined cost criteria and moving cells to alternate locations on the surface if necessary to satisfy the cost criteria. The cost criteria include a timing criterion based upon interconnect delay, where interconnect delay is modeled as a RC tree expressed as a function of pin-to-pin distance. The method accounts for driver to sink interconnect delay at the placement level, a novel aspect resulting from use of the RC tree model, which maximally utilizes available net information to produce an optimal timing estimate. Preferred versions utilize a RC tree interconnect delay model that is consistent with timing models used at design levels above placement, such as synthesis, and below placement, such as routing. Additionally, preferred versions can utilize either a constructive placement or iterative improvement placement method.

    摘要翻译： 一种用于在集成电路的表面上最佳地放置单元的方法，包括以下步骤：如果需要满足成本标准，将单元的布局与预定成本标准进行比较并将单元移动到表面上的替代位置。 成本标准包括基于互连延迟的定时标准，其中互连延迟被建模为作为针对针距离的函数的RC树。 该方法考虑了驱动程序以在布局级别中接收互连延迟，这是由使用RC树模型产生的新颖的方面，其最大限度地利用可用的网络信息来产生最佳的时序估计。 首选版本使用RC树互连延迟模型，其与在布局之上的设计级别（例如合成）以及在布局之下（例如路由）使用的定时模型一致。 另外，优选版本可以利用建设性位置或迭代改进放置方法。

    Advanced modular cell placement system
    8.
    发明授权
    Advanced modular cell placement system 失效
    先进的模块化放置系统

    公开(公告)号：US6067409A

    公开(公告)日：2000-05-23

    申请号：US798598

    申请日：1997-02-11

    申请人： Ranko Scepanovic ,  Ivan Pavisic ,  James S. Koford ,  Alexander E. Andreev ,  Edwin Jones

    发明人： Ranko Scepanovic ,  Ivan Pavisic ,  James S. Koford ,  Alexander E. Andreev ,  Edwin Jones

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5072

    摘要： A system for determining an affinity associated with relocating a cell located on a surface of a semiconductor chip to a different location on the surface is disclosed herein. Each cell may be part of a cell net containing multiple cells. The system initially defines a bounding box containing all cells in the net which contains the cell. The system then establishes a penalty vector based on the bounding box and borders of a region containing the cell, computes a normalized sum of penalties for all nets having the cell as a member, and calculates the affinity based on the normalized sum of penalties. Also included in the disclosed system are methods and apparatus for capacity and utilization planning of the use of the floor, or the surface area, and the methods and apparatus for parallelizing the process of affinity based placements using multiple processors. Finally, method and apparatus for connecting the cells based on a Steiner Tree method is disclosed.

    摘要翻译： 本文公开了一种用于确定与将位于半导体芯片的表面上的单元重新定位到表面上的不同位置的亲和度的系统。 每个细胞可以是包含多个细胞的细胞网的一部分。 系统最初定义了包含网络中包含单元格的所有单元格的边界框。 然后，该系统基于边界框和包含单元格的区域的边界来建立惩罚向量，计算具有该单元作为成员的所有网络的归一化惩罚总和，并且基于标准化的惩罚总和来计算亲和度。 所公开的系统中还包括用于使用楼层或表面积的容量和利用规划的方法和装置，以及用于使用多个处理器并行化基于亲和力的布置的过程的方法和装置。 最后，公开了基于Steiner Tree方法连接单元的方法和装置。

    Parallel processor implementation of net routing
    9.
    发明授权
    Parallel processor implementation of net routing 失效
    并行处理器实现网络路由

    公开(公告)号：US5930500A

    公开(公告)日：1999-07-27

    申请号：US798880

    申请日：1997-02-11

    申请人： Ranko Scepanovic ,  Edwin Jones ,  Alexander E. Andreev

    发明人： Ranko Scepanovic ,  Edwin Jones ,  Alexander E. Andreev

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5077

    摘要： A method for maximizing effectiveness of parallel processing, using multiple processors, to connect pins of a net of an integrated circuit is disclosed. The method requires the pins to be partitioned into sets of pins and the sets of pins to be further partitioned into meta-sets of the sets of pins. The sets and the meta-sets are connected using a minimal spanning tree algorithm, and the connected sets are made to share a pin, thereby ensuring that the whole net is interconnected without creating a loop in the routing. In addition, because the partitions and the sets of partitions average approximately the same number of pins, the work load can easily be balanced between the processors.

    摘要翻译： 公开了一种使多个处理器并联处理的有效性最大化的方法来连接集成电路网的引脚。 该方法需要将引脚分成一组引脚，并且该引脚组进一步划分成该组引脚的元组。 使用最小生成树算法连接集合和元集，并且使连接的集合共享引脚，从而确保整个网络互连而不在路由中创建环路。 另外，由于分区和分区的平均数大致相同，所以处理器之间可以容易地平衡工作负载。

    Advanced modular cell placement system
    10.
    发明授权
    Advanced modular cell placement system 有权

    公开(公告)号：US06292929B1

    公开(公告)日：2001-09-18

    申请号：US09444975

    申请日：1999-11-22

    申请人： Ranko Scepanovic ,  Ivan Pavisic ,  James S. Koford ,  Alexander E. Andreev ,  Edwin Jones

    发明人： Ranko Scepanovic ,  Ivan Pavisic ,  James S. Koford ,  Alexander E. Andreev ,  Edwin Jones

    IPC分类号： G06F1750

    摘要： A system for determining an affinity associated with relocating a cell located on a surface of a semiconductor chip to a different location on the surface is disclosed herein. Each cell may be part of a cell net containing multiple cells. The system initially defines a bounding box containing all cells in the net which contains the cell. The system then establishes a penalty vector based on the bounding box and borders of a region containing the cell, computes a normalized sum of penalties for all nets having the cell as a member, and calculates the affinity based on the normalized sum of penalties. Also included in the disclosed system are methods and apparatus for capacity and utilization planning of the use of the floor, or the surface area, and the methods and apparatus for parallelizing the process of affinity based placements using multiple processors. Finally, method and apparatus for connecting the cells based on a Steiner Tree method is disclosed.