公开(公告)号：US20190204893A1

公开(公告)日：2019-07-04

申请号：US15857802

申请日：2017-12-29

申请人： Efraim Rotem ,  Esfir Natanzon ,  Doron Rajwan ,  Eliezer Weissmann ,  Dorit Shapira ,  Lily P. Looi ,  Bart Plackle ,  Nadav Shulman

发明人： Efraim Rotem ,  Esfir Natanzon ,  Doron Rajwan ,  Eliezer Weissmann ,  Dorit Shapira ,  Lily P. Looi ,  Bart Plackle ,  Nadav Shulman

IPC分类号： G06F1/32 ,  G06F11/30 ,  G06F1/20

CPC分类号： G06F1/324 ,  G06F1/206 ,  G06F11/3024 ,  G06F11/3062

摘要： In one embodiment, a processor includes: at least one core; a stress detector coupled to the at least one core to receive at least one of a voltage and a temperature at which the processor is to operate, calculate an effective stress based at least in part thereon, and maintain an accumulated effective stress; a clock circuit to calculate a lifetime duration of the processor in a platform; a meter to receive the accumulated effective stress, the lifetime duration and a stress model value and generate a control signal based on a comparison of the accumulated effective stress and the stress model value; and a power controller to control at least one parameter of a turbo mode of the processor based at least in part on the control signal. Other embodiments are described and claimed.

公开(公告)号：US08539260B2

公开(公告)日：2013-09-17

申请号：US12798478

申请日：2010-04-05

申请人： Selim Bilgin ,  Lily P. Looi ,  Jeffrey C. Swanson

发明人： Selim Bilgin ,  Lily P. Looi ,  Jeffrey C. Swanson

IPC分类号： G06F1/26 ,  G06F1/32 ,  G06F15/16

CPC分类号： H04L12/12 ,  G06F1/3203 ,  H04L12/10

摘要： To address the need for power management, the following facilitates maintaining power states in an efficient manner based at least in part on managing packets at different layers of an input/output interface that supports multiple layers. One specific example prevents a destructive event for link layer control logic because packets and information might have been lost or dropped due to a hang condition and/or a dropped packet. In yet another example of power management, this facilitates a low power platform state by preventing the loss of packets or data upon exiting a platform power state upon initiation of a link reset condition by preventing certain types of packets from reaching link layer controller logic.

摘要翻译： 为了解决对电力管理的需要，以下有助于以至少部分地基于在支持多层的输入/输出接口的不同层处理分组的方式以有效的方式维持功率状态。 一个具体示例防止链路层控制逻辑的破坏性事件，因为由于挂起条件和/或丢弃的分组，分组和信息可能已经丢失或丢弃。 在功率管理的另一示例中，这通过防止在启动链路复位条件时通过防止某些类型的分组到达链路层控制器逻辑而退出平台功率状态时丢失分组或数据来促进低功率平台状态。

公开(公告)号：US08275560B2

公开(公告)日：2012-09-25

申请号：US12557263

申请日：2009-09-10

申请人： Sivakumar Radhakrishnan ,  Sin S. Tan ,  Stephan J. Jourdan ,  Lily P. Looi ,  Yi-Feng Liu

发明人： Sivakumar Radhakrishnan ,  Sin S. Tan ,  Stephan J. Jourdan ,  Lily P. Looi ,  Yi-Feng Liu

IPC分类号： G01R15/00 ,  G01R19/00 ,  G01R21/00 ,  G06F1/00

CPC分类号： G06F1/3203 ,  G06F1/3237 ,  Y02D10/128 ,  Y02D50/20

摘要： A method and system to enable power measurements of a system-on-chip in various modes. In one embodiment of the invention, the system-on-chip has full controllability of its logic and circuitry to facilitate configuration of the system-on-chip into a desired mode of operation. This allows hooks or interfaces to access the system-on-chip externally for measurements. For example, in one embodiment of the invention, the hooks in the system-on-chip allow a backend tester to configure the system-on-chip into various modes easily to perform power consumption measurements of one or more individual components of the system-on-chip. The power consumption measurement of the individual components in the system-on-chip can be performed faster and can be more accurate. In addition, the overall yield of the SOC can be increased as it is easier to detect failure parts.

摘要翻译： 一种能够以各种模式对片上系统进行功率测量的方法和系统。 在本发明的一个实施例中，片上系统具有其逻辑和电路的完全可控性，以便于将片上系统配置成期望的操作模式。 这允许钩子或接口在外部访问片上系统进行测量。 例如，在本发明的一个实施例中，片上系统中的钩子允许后端测试器将片上系统配置成各种模式，以便简单地执行系统级芯片的一个或多个单独部件的功耗测量， 片上 片上系统中各个组件的功耗测量可以更快地执行，并且可以更准确。 另外，由于易于检测故障部件，所以能够提高SOC的整体产量。

公开(公告)号：US20130054845A1

公开(公告)日：2013-02-28

申请号：US13222362

申请日：2011-08-31

申请人： Prashanth Nimmala ,  Robert J. Greiner ,  Lily P. Looi ,  Rupin H. Vakharwala ,  Marcus W. Song ,  James A. Beavens ,  Aimee D. Wood ,  Jeff V. Tran

发明人： Prashanth Nimmala ,  Robert J. Greiner ,  Lily P. Looi ,  Rupin H. Vakharwala ,  Marcus W. Song ,  James A. Beavens ,  Aimee D. Wood ,  Jeff V. Tran

IPC分类号： G06F13/14

CPC分类号： G06F13/4022 ,  G06F2213/0038

摘要： In one embodiment, the present invention includes apparatus that is formed on a single semiconductor die having one or more cores, a memory controller, and a hub coupled to the memory controller. The hub includes multiple fabrics each to communicate with a peripheral controller via a target interface and a master interface according to a first protocol, and where the fabrics are serially coupled via a first plurality of target interfaces in an upstream direction and a second plurality of target interfaces in a downstream direction. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括形成在具有一个或多个核心的单个半导体管芯上的装置，存储器控制器和耦合到存储器控制器的集线器。 集线器包括多个结构，每个结构根据第一协议经由目标接口和主接口与外围控制器通信，并且其中结构经由第一多个目标接口沿上游方向和第二多个目标 在下游方向接口。 描述和要求保护其他实施例。

公开(公告)号：US06615319B2

公开(公告)日：2003-09-02

申请号：US09752937

申请日：2000-12-29

申请人： Manoj Khare ,  Lily P. Looi ,  Akhilesh Kumar ,  Faye A. Briggs

发明人： Manoj Khare ,  Lily P. Looi ,  Akhilesh Kumar ,  Faye A. Briggs

IPC分类号： G06F1200

CPC分类号： G06F12/0822 ,  G06F12/082 ,  G06F12/0828 ,  G06F12/0831 ,  G06F2212/507

摘要： According to one embodiment, a method is disclosed. The method comprises receiving a read request from a first node in a multi-node computer system to read data from a memory at a second node. Subsequently, a write request from a third node is received to write data to the memory at the second node. The read request and write request is detected at conflict detection circuitry. Finally, read data from the memory at the second node is transmitted to the first node.

公开(公告)号：US07234029B2

公开(公告)日：2007-06-19

申请号：US09749660

申请日：2000-12-28

申请人： Manoj Khare ,  Faye A. Briggs ,  Akhilesh Kumar ,  Lily P. Looi ,  Kai Cheng

发明人： Manoj Khare ,  Faye A. Briggs ,  Akhilesh Kumar ,  Lily P. Looi ,  Kai Cheng

IPC分类号： G06F12/08 ,  G06F13/00

CPC分类号： G06F12/0817 ,  G06F12/0862 ,  G06F2212/2542 ,  G06F2212/507

摘要： A method for reducing memory latency in a multi-node architecture. In one embodiment, a speculative read request is issued to a home node before results of a cache coherence protocol are determined. The home node initiates a read to memory to complete the speculative read request. Results of a cache coherence protocol may be determined by a coherence agent to resolve cache coherency after the speculative read request is issued.

摘要翻译： 一种用于减少多节点架构中的存储器延迟的方法。 在一个实施例中，在确定高速缓存一致性协议的结果之前，向家庭节点发出推测性读请求。 家庭节点启动对存储器的读取以完成推测性读取请求。 高速缓存一致性协议的结果可以由相干代理确定，以在发布推测读请求之后解析高速缓存一致性。

公开(公告)号：US20150269109A1

公开(公告)日：2015-09-24

申请号：US14658026

申请日：2015-03-13

申请人： Bryan L. Spry ,  Su Wei Lim ,  Mikal C. Hunsaker ,  Rohit R. Verma ,  Lily P. Looi ,  Ronald W. Swartz ,  Michael W. Leddige ,  Vui Yong Liew

发明人： Bryan L. Spry ,  Su Wei Lim ,  Mikal C. Hunsaker ,  Rohit R. Verma ,  Lily P. Looi ,  Ronald W. Swartz ,  Michael W. Leddige ,  Vui Yong Liew

IPC分类号： G06F13/42 ,  G06F13/40

CPC分类号： G06F13/4221 ,  G06F13/122 ,  G06F13/4022 ,  G06F13/4265 ,  Y02D10/14 ,  Y02D10/151

摘要： Techniques and mechanisms for exchanging single-ended communications with a protocol stack of an integrated circuit package. In an embodiment, an integrated circuit (IC) chip includes a protocol stack comprising a transaction layer which performs operations compatible with a Peripheral Component Interconnect Express™ (PCIe™) specification. Transaction layer packets, exchanged between the transaction layer and a link layer of the protocol stack, are compatible with a PCIe™ format. In another embodiment, a physical layer of the protocol stack is to couple the IC chip to another IC chip for an exchange of the transaction layer packets via single-ended communications. A packaged device includes both of the IC chips.

摘要翻译： 用于与集成电路封装的协议栈交换单端通信的技术和机制。 在一个实施例中，集成电路（IC）芯片包括协议栈，其包括执行与外围组件互连Express（PCIe TM）规范兼容的操作的事务层。 在事务层和协议栈的链路层之间交换的事务层数据包与PCIe™格式兼容。 在另一个实施例中，协议栈的物理层是将IC芯片耦合到另一个IC芯片，用于通过单端通信交换事务层分组。 封装的器件包括两个IC芯片。

公开(公告)号：US20130336336A1

公开(公告)日：2013-12-19

申请号：US13971729

申请日：2013-08-20

申请人： Selim Bilgin ,  Lily P. Looi ,  Jeffrey C. Swanson

发明人： Selim Bilgin ,  Lily P. Looi ,  Jeffrey C. Swanson

IPC分类号： H04L12/12

CPC分类号： H04L12/12 ,  G06F1/3203 ,  H04L12/10

摘要： To address the need for power management, the following facilitates maintaining power states in an efficient manner based at least in part on managing packets at different layers of an input/output interface that supports multiple layers. One specific example prevents a destructive event for link layer control logic because packets and information might have been lost or dropped due to a hang condition and/or a dropped packet. In yet another example of power management, this facilitates a low power platform state by preventing the loss of packets or data upon exiting a platform power state upon initiation of a link reset condition by preventing certain types of packets from reaching link layer controller logic.

摘要翻译： 为了解决对电力管理的需要，以下有助于以至少部分地基于在支持多层的输入/输出接口的不同层处理分组的方式以有效的方式维持功率状态。 一个具体示例防止链路层控制逻辑的破坏性事件，因为由于挂起条件和/或丢弃的分组，分组和信息可能已经丢失或丢弃。 在功率管理的另一示例中，这通过防止在启动链路复位条件时通过防止某些类型的分组到达链路层控制器逻辑而退出平台功率状态时丢失分组或数据来促进低功率平台状态。

公开(公告)号：US20110246798A1

公开(公告)日：2011-10-06

申请号：US12798478

申请日：2010-04-05

申请人： Selim Bilgin ,  Lily P. Looi ,  Jeffrey C. Swanson

发明人： Selim Bilgin ,  Lily P. Looi ,  Jeffrey C. Swanson

IPC分类号： G06F1/32 ,  G06F15/16

CPC分类号： H04L12/12 ,  G06F1/3203 ,  H04L12/10

摘要： To address the need for power management, the following facilitates maintaining power states in an efficient manner based at least in part on managing packets at different layers of an input/output interface that supports multiple layers. One specific example prevents a destructive event for link layer control logic because packets and information might have been lost or dropped due to a hang condition and/or a dropped packet. In yet another example of power management, this facilitates a low power platform state by preventing the loss of packets or data upon exiting a platform power state upon initiation of a link reset condition by preventing certain types of packets from reaching link layer controller logic.

摘要翻译： 为了解决对电力管理的需要，以下有助于以至少部分地基于在支持多层的输入/输出接口的不同层处理分组的方式以有效的方式维持功率状态。 一个具体示例防止链路层控制逻辑的破坏性事件，因为由于挂起条件和/或丢弃的分组，分组和信息可能已经丢失或丢弃。 在功率管理的另一示例中，这通过防止在启动链路复位条件时通过防止某些类型的分组到达链路层控制器逻辑而退出平台功率状态时丢失分组或数据来促进低功率平台状态。

公开(公告)号：US07617329B2

公开(公告)日：2009-11-10

申请号：US10335001

申请日：2002-12-30

申请人： Tuan M. Quach ,  Lily P. Looi ,  Kai Cheng

发明人： Tuan M. Quach ,  Lily P. Looi ,  Kai Cheng

IPC分类号： G06F15/16

CPC分类号： G06F15/17375 ,  G06F12/0831

摘要： A system includes a scalability port switch (SPS) and a plurality of nodes. The SPS has a plurality of ports, each port coupled to a node. Each port is connected to a scalability port protocol distributed (SPPD). A snoop filter in the SPS tracks which nodes may be using various memory addresses. A scalability port protocol central (SPPC) is responsible for processing messages to support coherent and non-coherent transactions in the system.

摘要翻译： 系统包括可扩展性端口交换机（SPS）和多个节点。 SPS具有多个端口，每个端口耦合到一个节点。 每个端口连接到可扩展端口协议分发（SPPD）。 SPS中的监听滤波器跟踪哪些节点可能使用各种存储器地址。 可扩展性端口协议中心（SPPC）负责处理消息以支持系统中的一致和非一致性事务。