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公开(公告)号：US10977988B2
公开(公告)日：2021-04-13
申请号：US16838629
申请日：2020-04-02
Inventor： Woo Joo Lee , Suk Ho Lee , Kyung Jin Byun , Nak Woong Eum
IPC: G09G3/3208 , G09G3/20 , H05B45/37 , H05B45/00 , G06F1/3218 , G06F3/14 , G06F1/3296
Abstract: Provided is a display device including a display panel, a power delivery network (PDN), an image controller, and a PDN controller. The display panel may include a plurality of sub-panels. The PDN may be controlled by a control signal, respectively deliver voltages determined by the control signal to the plurality of sub-panels, and generate state information for determining the control signal. The image controller may receive to store frame image data, determine a number of frames to be integrated according to a window size, and integrate the frame image data of frames in the determined number into one image to generate integrated image data. The PDN controller may generate the control signal and a size adjusting signal based on the state information and the integrated image data, provide the generated control signal to the PDN, and may provide the generated size adjusting signal to the image controller. The size adjusting signal may adjust the window size.
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公开(公告)号：US09859889B2
公开(公告)日：2018-01-02
申请号：US15414236
申请日：2017-01-24
Inventor： Woojoo Lee , Young-Su Kwon , Kyung Jin Byun , Jin Ho Han , Nak Woong Eum
CPC classification number: H03K19/0013 , G06F3/0202 , H01L27/1104 , H01L29/49 , H03K17/9638 , H03K19/00369 , H03K19/0944
Abstract: An Ultra Low Voltage (ULV) digital circuit includes a logic circuit comprising a plurality of logic gates and a plurality of buffered interconnects for connecting between the plurality of logic gates, a temperature sensor configured to detect a temperature of the logic circuit, and a voltage controller configured to control a driving voltage provided to the logic circuit in order to reduce a power consumption of the logic circuit based on the detected temperature. Each of the plurality of logic gates and buffered interconnects reduces a signal delay as a temperature increases.
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公开(公告)号：US10180904B2
公开(公告)日：2019-01-15
申请号：US15241902
申请日：2016-08-19
Inventor： Jin Ho Han , Young-Su Kwon , Kyung Jin Byun , Nak Woong Eum
IPC: G06F12/08 , G06F12/0811 , G06F12/084 , G06F12/0842 , G06F12/0875
Abstract: Provided is a cache memory. The cache memory includes a first to Nth level-1 caches configured to correspond to first to Nth cores, respectively, a level-2 sharing cache configured to be shared by the first to Nth level-1 caches, and a coherence controller configured to receive an address from each of the first to Nth cores and allocate at least a partial area in an area of the level-2 sharing cache to one of the first to Nth level-1 caches based on the received address.
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公开(公告)号：US10013310B2
公开(公告)日：2018-07-03
申请号：US15241808
申请日：2016-08-19
Inventor： Jin Ho Han , Young-Su Kwon , Kyoung Seon Shin , Kyung Jin Byun , Nak Woong Eum
IPC: G06F11/10 , G06F12/08 , G06F12/0804 , G06F12/0895
CPC classification number: G06F11/1076 , G06F11/1044 , G06F12/0804 , G06F12/0808 , G06F12/0864 , G06F12/0895 , G06F12/0897 , G06F2212/1032 , Y02D10/13
Abstract: Provided is an operating method of a cache memory device includes receiving an address from an external device, reading an entry corresponding to at least a portion of the received address among a plurality of entries that are included in the cache memory, performing error detection on additional information that is included in the read entry, and performing a recovery operation on the entry based on a result of error detection and the additional information. The entry includes the additional information and a cache line corresponding to the additional information, and the additional information includes a tag, valid bit, and dirty bit that correspond to the cache line.
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公开(公告)号：US10002009B2
公开(公告)日：2018-06-19
申请号：US15408210
申请日：2017-01-17
Inventor： Jae-Jin Lee , Hyeong Uk Jang , Kyung Jin Byun , Nak Woong Eum
CPC classification number: G06F9/455 , G06F9/4451 , G06F16/258 , G06F16/90335 , G06F21/00 , G06F21/53 , G06F21/88
Abstract: An electronic device configured to perform forensic analysis on a target device includes a data extractor, an emulator, and a user data converter. The data extractor obtains, from the target device, a source file of at least one of applications installed on the target device. The data extractor obtains, from the target device, user data generated according to the least one of the applications being executed in the target device. The emulator emulates an execution of a target application installed based on the obtained source file. The user data converter converts the obtained user data having a data structure according to a database scheme of the target device into converted user data having a data structure according to a database scheme of the emulator. The emulator emulates the execution of the target application such that the target application operates using the converted user data.
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Patent Agency Ranking
公开(公告)号：US09529654B2
公开(公告)日：2016-12-27
申请号：US14547301
申请日：2014-11-19
Inventor： Young Su Kwon , Jin Ho Han , Kyung Jin Byun
CPC classification number: G06F11/0772 , G06F11/0721 , G06F11/183
Abstract: A recoverable and fault-tolerant CPU core and a control method thereof are provided. The recoverable and fault-tolerant CPU core includes first, second, and third arithmetic logic circuits configured to perform a calculation requested by the same instruction, a first selector configured to compare calculation values output from the first, second, and third arithmetic logic circuits by the same instruction, determine as a normal state when two or more of the calculation values are the same, and if not, determine as a fault state, and a register file configured to record the calculation value having the same value, when determining as the normal state in the first selector.
Abstract translation: 提供了一种可恢复和容错的CPU内核及其控制方法。 可恢复和容错CPU核心包括被配置为执行由相同指令请求的计算的第一，第二和第三算术逻辑电路，第一选择器被配置为将从第一，第二和第三算术逻辑电路输出的计算值与 相同的指令，当两个或多个计算值相同时确定为正常状态，如果不是，则确定为故障状态，以及配置为记录具有相同值的计算值的寄存器文件，当确定为 第一选择器中的正常状态。
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公开(公告)号：US12267631B2
公开(公告)日：2025-04-01
申请号：US17399603
申请日：2021-08-11
Inventor： Sukho Lee , Sang Pil Kim , Young Hwan Bae , Jae-Jin Lee , Kyuseung Han , Tae Wook Kang , Sung Eun Kim , Hyuk Kim , Kyung Hwan Park , Hyung-Il Park , Kyung Jin Byun , Kwang Il Oh , In Gi Lim
IPC: H04N7/52 , H04N7/01 , H04N7/08 , H04N7/088 , H04N21/236 , H04N21/488 , H04N5/278
Abstract: Disclosed is a network-on-chip including a first data converter that receives first image data and second image data from at least one image sensor and encodes one image data among the first image data and the second image data, into first data, based on whether the first image data is identical to the second image data and a second data converter that receives non-image data from at least one non-image sensor and encodes the received non-image data into second data. The network-on-chip outputs the first data and the second data to transmit the first data and the second data to an external server at a burst length.
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8.发明授权公开(公告)号：US11923882B2
公开(公告)日：2024-03-05
申请号：US17212252
申请日：2021-03-25
Inventor： Tae Wook Kang , Sung Eun Kim , Hyung-Il Park , Jae-Jin Lee , Hyuk Kim , Kyung Hwan Park , Mi Jeong Park , Kyung Jin Byun , Kwang Il Oh , In Gi Lim
CPC classification number: H04B1/18 , H04B5/0031 , H04B13/005
Abstract: A hybrid communication device, an operation method thereof, and a communication system including the same are provided. The hybrid communication device includes a contact unit that includes an antenna for receiving a first communication signal and an electrode for receiving a second signal, a switch controller that includes a first switch and a second switch and controls the first switch and the second switch based on a change in capacitance of the electrode, and a signal processing unit that receives at least one of the first communication signal and the second communication signal from the contact unit via the first switch and processes the received signal. The first switch is connected to the contact unit, and the signal processing unit is connected to the first switch.
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公开(公告)号：US10057583B2
公开(公告)日：2018-08-21
申请号：US15232542
申请日：2016-08-09
Inventor： Sukho Lee , Kyung Jin Byun , Nak Woong Eum
IPC: H04N19/159 , H04N19/176 , H04N19/182 , H04N19/122 , H04N19/61 , H04N19/124 , H04N19/13 , H04N19/96
CPC classification number: H04N19/159 , H04N19/11 , H04N19/122 , H04N19/124 , H04N19/13 , H04N19/176 , H04N19/182 , H04N19/463 , H04N19/61 , H04N19/96
Abstract: Provided is an encoding method of an image encoding device including predicting an intra mode for coding blocks of a minimum size for intra prediction to generate an intra pixel; and using the intra mode of the coding blocks of the minimum size to restore an intra mode of coding blocks of a larger size.
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公开(公告)号：US09836401B2
公开(公告)日：2017-12-05
申请号：US15222940
申请日：2016-07-28
Inventor： Jae-Jin Lee , Kyung Jin Byun , Nak Woong Eum
IPC: G06F12/08 , G06F12/084 , G06F9/30 , G06F12/0842 , G06F12/0875
CPC classification number: G06F12/084 , G06F9/3017 , G06F12/0842 , G06F12/0875 , G06F17/5022 , G06F2212/452 , G06F2212/62 , G06F2217/68
Abstract: Provided is a multi-core simulation method including allocating, to a working memory, a shared translation block cache commonly used for a plurality of core models, reading a first target instruction to be performed in a first core model, generating a first translation block corresponding to the first target instruction and provided with an instruction set used in a host processor, performing the first translation block in the first core model after the first translation block is stored in the shared translation block cache, reading a second target instruction to be performed in a second core model, searching the shared translation block cache for a translation block including same content as that of the second target instruction, and performing the first translation block in the second core model, when the first target instruction includes same content as that of the second target instruction.
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