公开(公告)号：US07302376B2

公开(公告)日：2007-11-27

申请号：US10248853

申请日：2003-02-25

申请人： Eric Adler ,  Serge Biesemans ,  Micah S. Galland ,  Terence B. Hook ,  Judith H. McCullen ,  Eric S. Phipps ,  James A. Slinkman

发明人： Eric Adler ,  Serge Biesemans ,  Micah S. Galland ,  Terence B. Hook ,  Judith H. McCullen ,  Eric S. Phipps ,  James A. Slinkman

IPC分类号： G06F17/50

CPC分类号： G03F1/36 ,  G06F17/5036 ,  G06F17/5068

摘要： A method for calibrating a software model for a given structure of interest for a variable imposed by an adjacent structure. First determine the spatial extent of the variable imposed by the adjacent structure. Then assign a value to the spatial extent, which varies as a function of distance from the adjacent structure to the given structure. Finally, attach that value to the model of the given structure.

摘要翻译： 一种用于校正由相邻结构施加的变量的给定感兴趣结构的软件模型的方法。 首先确定相邻结构施加的变量的空间范围。 然后为空间范围分配一个值，该空间范围随着从相邻结构到给定结构的距离的函数而变化。 最后，将该值附加到给定结构的模型中。

公开(公告)号：US08619979B2

公开(公告)日：2013-12-31

申请号：US12823278

申请日：2010-06-25

申请人： Joel T. Ficke ,  William E. Hall ,  Terence B. Hook ,  Michael A. Sperling ,  Larry Wissel

发明人： Joel T. Ficke ,  William E. Hall ,  Terence B. Hook ,  Michael A. Sperling ,  Larry Wissel

IPC分类号： G06F21/73 ,  H04L9/08

CPC分类号： G06F21/73 ,  H04L9/08 ,  H04L9/0866 ,  H04L9/3278

摘要： Electronic devices and methods are disclosed to provide and to test a physically unclonable function (PUF) based on relative threshold voltages of one or more pairs of transistors. In a particular embodiment, an electronic device is operable to generate a response to a challenge. The electronic device includes a plurality of transistors, with each of the plurality of transistors having a threshold voltage substantially equal to an intended threshold voltage. The electronic device includes a challenge input configured to receive the challenge. The challenge input includes one or more bits that are used to individually select each of a pair of transistors of the plurality of transistors. The electronic device also includes a comparator to receive an output voltage from each of the pair of transistors and to generate a response indicating which of the pair of transistors has the higher output voltage. The output voltage of each of the pair of transistors varies based on the threshold voltage of each of the pair of transistors.

摘要翻译： 公开了电子装置和方法，以基于一对或多对晶体管的相对阈值电压来提供和测试物理上不可克隆的功能（PUF）。 在特定实施例中，电子设备可操作以产生对挑战的响应。 电子设备包括多个晶体管，多个晶体管中的每一个具有基本上等于预期阈值电压的阈值电压。 电子设备包括被配置为接收挑战的挑战输入。 挑战输入包括用于单独选择多个晶体管中的一对晶体管中的每一个的一个或多个位。 该电子设备还包括一个比较器，用于接收来自该对晶体管中的每一个的输出电压，并产生一个响应，该响应指示该对晶体管中的哪一个具有较高的输出电压。 该对晶体管中的每一个晶体管的输出电压根据该晶体管对的阈值电压而变化。

公开(公告)号：US20130256748A1

公开(公告)日：2013-10-03

申请号：US13431414

申请日：2012-03-27

申请人： William F. Clark, JR. ,  Robert J. Gauthier, JR. ,  Terence B. Hook ,  Junjun Li ,  Theodorus E. Standaert ,  Thomas A. Wallner

发明人： William F. Clark, JR. ,  Robert J. Gauthier, JR. ,  Terence B. Hook ,  Junjun Li ,  Theodorus E. Standaert ,  Thomas A. Wallner

IPC分类号： H01L29/73 ,  G06F17/50 ,  H01L21/331

CPC分类号： H01L27/1211 ,  H01L21/7624 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0207 ,  H01L27/0262 ,  H01L27/0924 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/785

摘要： Device structures, design structures, and fabrication methods for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A device region is formed in a trench and is coupled with a handle wafer of a semiconductor-on-insulator substrate. The device region extends through a buried insulator layer of the semiconductor-on-insulator substrate toward a top surface of a device layer of the semiconductor-on-insulator substrate. The device region is comprised of lightly-doped semiconductor material. The device structure further includes a doped region formed in the device region and that defines a junction. A portion of the device region is laterally positioned between the doped region and the buried insulator layer of the semiconductor-on-insulator substrate. Another region of the device layer may be patterned to form fins for fin-type field-effect transistors.

摘要翻译： 无源器件的器件结构，设计结构和制造方法可用作鳍式场效应晶体管集成电路技术中的静电放电保护器件。 器件区域形成在沟槽中并且与绝缘体上半导体衬底的处理晶片耦合。 器件区域延伸穿过绝缘体上半导体衬底的掩埋绝缘体层朝向绝缘体上半导体衬底的器件层的顶表面。 器件区域由轻掺杂的半导体材料组成。 器件结构还包括形成在器件区域中并限定结的掺杂区域。 器件区域的一部分横向地位于绝缘体上半导体衬底的掺杂区域和掩埋绝缘体层之间。 可以对器件层的另一区域进行构图以形成翅片型场效应晶体管的鳍片。

公开(公告)号：US08513106B2

公开(公告)日：2013-08-20

申请号：US12964082

申请日：2010-12-09

申请人： Terence B. Hook

发明人： Terence B. Hook

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L29/78648

摘要： Butted p-n junctions interconnecting back gates in an SOI process, methods for making butted p-n junctions, and design structures. The butted junction includes an overlapping region formed in the bulk substrate by overlapping the mask windows of the ion-implantation masks used to form the back gates. A damaged region may be selectively formed to introduce mid-gap energy levels in the semiconductor material of the overlapping region employing one of the implantation masks used to form the back gates. The damage region causes the butted junction to be leaky and conductively couples the overlapped back gates to each other and to the substrate. Other back gates may be formed that are floating and not coupled to the substrate.

公开(公告)号：US20120299080A1

公开(公告)日：2012-11-29

申请号：US13114283

申请日：2011-05-24

申请人： Robert H. Dennard ,  Terence B. Hook

发明人： Robert H. Dennard ,  Terence B. Hook

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L27/1203 ,  H01L21/823878 ,  H01L21/823892 ,  H01L21/84

摘要： A structure includes a semiconductor substrate having a first type of conductivity and a top surface; an insulating layer disposed over the top surface; a semiconductor layer disposed over the insulating layer and a plurality of transistor devices disposed upon the semiconductor layer. Each transistor device includes a source, a drain and a gate stack defining a channel between the source and the drain, where some transistor devices have a first type of channel conductivity and the remaining transistor devices have a second type of channel conductivity. The structure further includes a well region formed adjacent to the top surface of the substrate and underlying the plurality of transistor devices, the well region having a second type of conductivity and extending to a first depth within the substrate. The structure further includes first isolation regions between adjacent transistor devices and extending through the semiconductor layer to a depth sufficient for electrically isolating the adjacent transistor devices from one another, and second isolation regions between selected adjacent transistor devices. The second isolation regions extend through the silicon layer, through the insulating layer and into the substrate to a second depth that is greater than the first depth to electrically separate the well region into a first well region and a second well region. The structure further includes at least one back gate region disposed wholly within a well region and underlying one of the plurality of transistor devices, the at least one back gate region has the first type of conductivity and is electrically floating within the well region, where during operation the at least one back gate region having the first type of conductivity is biased by leakage and capacitive coupling by a bias potential applied to the well region within which it is disposed.

摘要翻译： 一种结构包括具有第一类导电性的半导体衬底和顶表面; 设置在所述顶表面上的绝缘层; 设置在所述绝缘层上的半导体层和设置在所述半导体层上的多个晶体管器件。 每个晶体管器件包括源极，漏极和限定在源极和漏极之间的沟道的栅极堆叠，其中一些晶体管器件具有第一类型的沟道导电性，并且剩余的晶体管器件具有第二类型的沟道导电性。 所述结构还包括邻近所述衬底的顶表面形成并位于所述多个晶体管器件下方的阱区，所述阱区具有第二类型的导电性并延伸到所述衬底内的第一深度。 该结构还包括相邻晶体管器件之间的第一隔离区域，并延伸穿过半导体层至足以将相邻晶体管器件彼此电绝缘的深度以及所选择的相邻晶体管器件之间的第二隔离区域。 第二隔离区延伸穿过硅层，穿过绝缘层并进入衬底至比第一深度更大的第二深度，以将阱区电分离成第一阱区和第二阱区。 该结构还包括至少一个背栅极区域，其完全设置在阱区域内并且位于多个晶体管器件中的一个之下，所述至少一个背栅极区域具有第一类型的导电性并且在阱区域内电浮动， 操作具有第一类型的导电性的至少一个背栅极区域被施加到其所配置的阱区域的偏置电位的泄漏和电容耦合偏置。

公开(公告)号：US20110317829A1

公开(公告)日：2011-12-29

申请号：US12823278

申请日：2010-06-25

申请人： Joel T. Ficke ,  William E. Hall ,  Terence B. Hook ,  Michael A. Sperling ,  Larry Wissel

发明人： Joel T. Ficke ,  William E. Hall ,  Terence B. Hook ,  Michael A. Sperling ,  Larry Wissel

IPC分类号： H04L9/20

CPC分类号： G06F21/73 ,  H04L9/08 ,  H04L9/0866 ,  H04L9/3278

摘要： Electronic devices and methods are disclosed to provide and to test a physically unclonable function (PUF) based on relative threshold voltages of one or more pairs of transistors. In a particular embodiment, an electronic device is operable to generate a response to a challenge. The electronic device includes a plurality of transistors, with each of the plurality of transistors having a threshold voltage substantially equal to an intended threshold voltage. The electronic device includes a challenge input configured to receive the challenge. The challenge input includes one or more bits that are used to individually select each of a pair of transistors of the plurality of transistors. The electronic device also includes a comparator to receive an output voltage from each of the pair of transistors and to generate a response indicating which of the pair of transistors has the higher output voltage. The output voltage of each of the pair of transistors varies based on the threshold voltage of each of the pair of transistors.

摘要翻译： 公开了电子装置和方法，以基于一对或多对晶体管的相对阈值电压来提供和测试物理上不可克隆的功能（PUF）。 在特定实施例中，电子设备可操作以产生对挑战的响应。 电子设备包括多个晶体管，多个晶体管中的每一个具有基本上等于预期阈值电压的阈值电压。 电子设备包括被配置为接收挑战的挑战输入。 挑战输入包括用于单独选择多个晶体管中的一对晶体管中的每一个的一个或多个位。 该电子设备还包括一个比较器，用于接收来自该对晶体管中的每一个的输出电压，并产生一个响应，该响应指示该对晶体管中的哪一个具有较高的输出电压。 该对晶体管中的每一个晶体管的输出电压根据该晶体管对的阈值电压而变化。

公开(公告)号：US20100013026A1

公开(公告)日：2010-01-21

申请号：US12173407

申请日：2008-07-15

申请人： Roger Allen Booth, JR. ,  Kangguo Cheng ,  Terence B. Hook

发明人： Roger Allen Booth, JR. ,  Kangguo Cheng ,  Terence B. Hook

IPC分类号： H01L27/02 ,  H01L21/22

CPC分类号： H01L27/0629 ,  H01L28/20

摘要： The fabrication of integrated circuits comprising resistors having the same structure but different sheet resistances is disclosed herein. In one embodiment, a method of fabricating an integrated circuit comprises: concurrently forming a first resistor laterally spaced from a second resistor above or within a semiconductor substrate, the first and second resistors comprising a doped semiconductive material; depositing a dopant receiving material across the first and second resistors and the semiconductor substrate; removing the dopant receiving material from upon the first resistor while retaining the dopant receiving material upon the second resistor; and annealing the first and second resistors to cause a first sheet resistance of the first resistor to be different from a second sheet resistance of the second resistor.

摘要翻译： 本文公开了包括具有相同结构但具有不同薄层电阻的电阻器的集成电路的制造。 在一个实施例中，一种制造集成电路的方法包括：与半导体衬底之上或之内的第二电阻器横向隔开的第一电阻器同时形成，所述第一和第二电阻器包括掺杂的半导体材料; 在第一和第二电阻器和半导体衬底上沉积掺杂剂接收材料; 在所述第一电阻器上移除所述掺杂剂接收材料，同时将所述掺杂剂接收材料保持在所述第二电阻器上; 以及使所述第一和第二电阻器退火以使所述第一电阻器的第一薄层电阻与所述第二电阻器的第二薄层电阻不同。

公开(公告)号：US20090174008A1

公开(公告)日：2009-07-09

申请号：US11970579

申请日：2008-01-08

申请人： Deleep R. Nair ,  Terence B. Hook

发明人： Deleep R. Nair ,  Terence B. Hook

IPC分类号： H01L27/06 ,  H01L21/8234

CPC分类号： H01L27/0266 ,  H01L29/78

摘要： Protecting a FET from plasma damage during FEOL processing by forming a FET-like structure in conjunction with and adjacent to an FET, in a same well as the FET, but having a body doped opposite to the well polarity. The FET-like structure is formed with thinner oxide than the gate oxide of the FET, has a gate structure (poly) connected with the gate of the FET, and may be shorted out by the first metal layer (M1).

摘要翻译： 通过在与FET相同的FET中与FET结合并与FET相邻并且具有与阱极性相反的掺杂体，在FEOL处理期间保护FET免受等离子体损伤。 FET型结构形成为具有比FET的栅极氧化物更薄的氧化物，具有与FET的栅极连接的栅极结构（poly），并且可以被第一金属层（M1）短路。

公开(公告)号：US20080116527A1

公开(公告)日：2008-05-22

申请号：US11561537

申请日：2006-11-20

申请人： Terence B. Hook ,  Jeffrey B. Johnson ,  Yoo-Mi Lee

发明人： Terence B. Hook ,  Jeffrey B. Johnson ,  Yoo-Mi Lee

IPC分类号： H01L27/088 ,  H01L21/8234

CPC分类号： H01L27/088 ,  H01L21/823437 ,  H01L27/0207

摘要： Methods of improving operational parameters between at least a pair of matched transistors, and a set of transistors, are disclosed. One embodiment of a method includes a method of improving at least one of a threshold voltage (Vt) mismatch and current drive between at least a pair of matched transistors for analog applications, the method comprising: forming at least a pair of transistors, each with a gate having a plurality of connected fingers; and optimizing a total length of a channel under the plurality of fingers to attain at least one of: a) a reduced threshold voltage mismatch between the at least pair of transistors, and b) increased current drive for a given threshold voltage mismatch, between the at least pair of transistors, each finger having a length less than an overall length of the channel.

摘要翻译： 公开了改善至少一对匹配晶体管之间的操作参数的方法和一组晶体管。 方法的一个实施例包括一种改进用于模拟应用的至少一对匹配晶体管之间的阈值电压（Vt）失配和电流驱动中的至少一个的方法，所述方法包括：形成至少一对晶体管，每个晶体管具有 具有多个连接的手指的门; 以及优化所述多个指状物下的通道的总长度以达到以下至少一个：a）所述至少一对晶体管之间的阈值电压失配降低，以及b）对于给定阈值电压失配的增加的电流驱动， 至少一对晶体管，每个手指的长度小于通道的总长度。

公开(公告)号：US07098513B2

公开(公告)日：2006-08-29

申请号：US10905682

申请日：2005-01-17

申请人： Kiran V. Chatty ,  Robert J. Gauthier ,  Terence B. Hook ,  Christopher S. Putnam ,  Mujahid Muhammad

发明人： Kiran V. Chatty ,  Robert J. Gauthier ,  Terence B. Hook ,  Christopher S. Putnam ,  Mujahid Muhammad

IPC分类号： H01L29/76

CPC分类号： H01L29/78 ,  H01L27/027

摘要： A field effect transistor with associated parasitic lateral npn bipolar junction transistor includes a source region in a substrate, a channel region in the substrate laterally adjacent to the source region, a drain region in the substrate laterally adjacent to the channel region, and a gate above the channel region of the substrate. In addition, a reduced trigger voltage region of the substrate is positioned below the drain region. The reduced trigger voltage region has a threshold voltage of about zero and comprises an undoped region of the pure wafer substrate. Thus, the reduced trigger voltage region is free of implanted N-type and P-type doping.

摘要翻译： 具有相关联的寄生横向npn双极结型晶体管的场效应晶体管包括衬底中的源极区域，与源极区域横向相邻的衬底中的沟道区域，衬底中的与沟道区域横向相邻的漏极区域，以及位于 衬底的沟道区域。 此外，衬底的降低的触发电压区域位于漏极区域的下方。 降低的触发电压区域具有约零的阈值电压，并且包括纯晶片衬底的未掺杂区域。 因此，降低的触发电压区域没有注入的N型和P型掺杂。