公开(公告)号：US06976204B1

公开(公告)日：2005-12-13

申请号：US09882417

申请日：2001-06-15

Applicant: Eric G. Chambers ,  James R. Magro ,  Dan S. Mudgett

Inventor： Eric G. Chambers ,  James R. Magro ,  Dan S. Mudgett

IPC: G11C7/10 ,  G11C29/00 ,  H03M13/00

CPC classification number: G11C7/1039 ,  G06F11/106 ,  G11C7/1006

Abstract: A circuit and method for correcting erroneous data in memory for pipelined reads. A memory controller includes a control unit, a storage unit and an error detection and correction unit. The control unit is configured to read data including an associated error correction code from a memory subsystem in response to a memory read request. The error detection and correction unit is coupled to receive the data and configured to determine whether an error exists in that data based upon the associated error correction code. The control unit is configured to store an indication in the storage unit that the data corresponding to the memory read request is erroneous. The control unit is further configured to detect the indication in the storage unit and to responsively perform a subsequent read of the data from the memory subsystem and to write a corrected version of the data back to the memory subsystem.

Abstract translation: 一种用于校正用于流水线读取的存储器中的错误数据的电路和方法。 存储器控制器包括控制单元，存储单元和错误检测和校正单元。 控制单元被配置为响应于存储器读取请求从存储器子系统读取包括相关联的纠错码的数据。 错误检测和校正单元被耦合以接收数据并被配置为基于相关联的纠错码来确定该数据中是否存在错误。 控制单元被配置为在存储单元中存储与存储器读取请求相对应的数据是错误的指示。 控制单元还被配置为检测存储单元中的指示并且响应地执行来自存储器子系统的数据的后续读取并将该数据的校正版本写回到存储器子系统。

公开(公告)号：US06968417B1

公开(公告)日：2005-11-22

申请号：US10103214

申请日：2002-03-21

Applicant: Eric G. Chambers ,  Tahsin Askar

Inventor： Eric G. Chambers ,  Tahsin Askar

IPC: G06F13/12 ,  G06F13/36 ,  G06F13/42

CPC classification number: G06F13/122 ,  G06F13/4265

Abstract: A method and apparatus for reducing latency in a peripheral interface circuit of an I/O node of a computer system. The apparatus includes a buffer coupled to a control unit. The buffer may be configured to receive data on a first bus and the control unit may be configured to generate a first command type in response to receiving a first quantity of data having invalid bytes within the buffer. The control unit may be further configured to generate a second command type in response to a receiving within the buffer a second quantity of data having no invalid bytes. Further, in response to receiving a particular transaction type, the control unit may be configured to generate the second command type before the first quantity of data is received within the buffer.

Abstract translation: 一种用于减少计算机系统的I / O节点的外围接口电路中的等待时间的方法和装置。 该装置包括耦合到控制单元的缓冲器。 缓冲器可以被配置为在第一总线上接收数据，并且控制单元可以被配置为响应于在缓冲器中接收到具有无效字节的第一数量的数据来生成第一命令类型。 控制单元还可以被配置为响应于在缓冲器内的接收而产生第二数量的无效字节的第二命令类型。 此外，响应于接收到特定交易类型，控制单元可以被配置为在缓冲器内接收到第一数据量之前生成第二命令类型。

公开(公告)号：US06725297B1

公开(公告)日：2004-04-20

申请号：US10093146

申请日：2002-03-07

Applicant: Tahsin Askar ,  Larry D. Hewitt ,  Eric G. Chambers

Inventor： Tahsin Askar ,  Larry D. Hewitt ,  Eric G. Chambers

IPC: G06F1300

CPC classification number: G06F13/128

Abstract: A peripheral interface circuit for an I/O node of a computer system. A peripheral interface circuit for an input/output node of a computer system includes a first buffer circuit, a second buffer circuit and a bus interface circuit. The first buffer circuit receives packet commands and may include a first plurality of buffers each corresponding to a respective virtual channel of a plurality of virtual channels. The second buffer circuit is coupled to receive packet commands from the bus interface circuit and may include a second plurality of buffers each corresponding to a respective virtual channel of the plurality of virtual channels. The bus interface circuit may be configured to translate selected packet commands stored in the first buffer circuit into commands suitable for transmission on a peripheral bus.

Abstract translation: 用于计算机系统的I / O节点的外围接口电路。 一种用于计算机系统的输入/输出节点的外围接口电路包括第一缓冲电路，第二缓冲电路和总线接口电路。 第一缓冲电路接收分组命令，并且可以包括每个对应于多个虚拟通道的相应虚拟通道的第一多个缓冲器。 第二缓冲电路被耦合以从总线接口电路接收分组命令，并且可以包括每个对应于多个虚拟通道中的相应虚拟通道的第二多个缓冲器。 总线接口电路可以被配置为将存储在第一缓冲器电路中的选择的分组命令转换成适合于在外围总线上传输的命令。

公开(公告)号：US06883045B1

公开(公告)日：2005-04-19

申请号：US10093124

申请日：2002-03-07

Applicant: Tahsin Askar ,  Eric G. Chambers

Inventor： Tahsin Askar ,  Eric G. Chambers

IPC: G06F13/12 ,  G06F13/00

CPC classification number: G06F13/128

Abstract: An apparatus for reordering graphics responses in a peripheral interface circuit for an I/O node of a computer system. The apparatus includes a data buffer and a control unit. The data buffer includes a first plurality of storage locations each corresponding to one of a plurality of tag values. The data buffer may receive a plurality of data packets associated with the graphics transactions. The data buffer may also store the data packets in the storage locations according to tag values. The control unit includes a storage unit having a second plurality of locations. Each of the locations in the storage unit corresponds to one of the tag values and may provide an indication of whether a given data packet has been stored in the data buffer. The control unit may further determine an order in which the plurality of data packets is read from the data buffer.

Abstract translation: 一种用于在计算机系统的I / O节点的外围接口电路中重新排序图形响应的装置。 该装置包括数据缓冲器和控制单元。 数据缓冲器包括每个对应于多个标签值之一的第一多个存储位置。 数据缓冲器可以接收与图形事务相关联的多个数据分组。 数据缓冲器还可以根据标签值将数据包存储在存储位置。 控制单元包括具有第二多个位置的存储单元。 存储单元中的每个位置对应于标签值之一，并且可以提供给定数据分组是否已经存储在数据缓冲器中的指示。 控制单元还可以从数据缓冲器中确定读取多个数据分组的顺序。

公开(公告)号：US06996657B1

公开(公告)日：2006-02-07

申请号：US10103238

申请日：2002-03-21

Applicant: Eric G. Chambers ,  Tahsin Askar

Inventor： Eric G. Chambers ,  Tahsin Askar

IPC: G06F12/36

CPC classification number: G06F13/4247 ,  G06F12/0815

Abstract: An apparatus for providing packets in a peripheral interface circuit of an I/O node of a computer system. The apparatus includes a buffer that may be configured to accumulate data received on a first bus. The apparatus further includes a control unit coupled to the buffer which may be configured to transmit a data packet containing a first number of bytes of the data in response to detecting that any of the bytes of the data is invalid. The control unit may be further configured to transmit the data packet containing a second number of bytes of the data in response to detecting that all of the bytes are valid.

Abstract translation: 一种用于在计算机系统的I / O节点的外围接口电路中提供分组的装置。 该装置包括可被配置为累积在第一总线上接收的数据的缓冲器。 该装置还包括耦合到缓冲器的控制单元，其可以被配置为响应于检测到数据的任何字节无效而发送包含数据的第一数量字节的数据分组。 响应于检测到所有字节都是有效的，控制单元还可以被配置为发送包含数据的第二数量字节的数据分组。

公开(公告)号：US06327259B1

公开(公告)日：2001-12-04

申请号：US09088788

申请日：1998-06-01

Applicant: Kenny Kok-Hoong Chiu ,  Eric G. Chambers ,  Patrick E. Maupin

Inventor： Kenny Kok-Hoong Chiu ,  Eric G. Chambers ,  Patrick E. Maupin

IPC: H04J300

CPC classification number: G06F13/372 ,  H04J3/0605 ,  H04J3/1682

Abstract: A microcontroller is provided with one or more synchronous serial channels, such as HDLC channels, that are coupled to time slot assigners for communication over a time division multiplex bus. The time slot assigners each include a bit position start register and a bit position stop register that allows the time slot assigner to enable and disable the associated synchronous serial channel on the arrival of a specific bit position within the time division multiplex bus frame. Further, an end of slot adjust register provides for additional bits to be placed by the time slot assigner on to the end of a slot that is transmitted by an associated synchronous serial communication channel transmitter.

Abstract translation: 微控制器被提供有一个或多个同步串行通道，例如HDLC通道，其耦合到时隙分配器，用于通过时分复用总线进行通信。 时隙分配器各自包括位位置开始寄存器和位位置停止寄存器，其允许时隙分配器在时分多路复用总线帧中的特定位位置到达时启用和禁用相关联的同步串行通道。 此外，时隙调整寄存器的结尾提供由时隙分配器放置到相关联的同步串行通信信道发射机发送的时隙的末端的附加比特。

公开(公告)号：US5862148A

公开(公告)日：1999-01-19

申请号：US798249

申请日：1997-02-11

Applicant: Melanie D. Typaldos ,  Eric G. Chambers ,  Wade L. Williams

Inventor： Melanie D. Typaldos ,  Eric G. Chambers ,  Wade L. Williams

IPC: G06F11/36 ,  G06F11/00

CPC classification number: G06F11/3656

Abstract: A microcontroller integrates an internal memory accessible by the cores included thereon. Logic within the microcontroller compares memory addresses generated by the cores to values in a configuration register specifying a memory address range in which the internal memory resides. The logic generates a chip select signal to the internal memory if the memory address generated resides within the specified address range to enable accesses by the cores to the internal memory. The integrated circuit may be configured in a debug mode wherein the chip select signal is inhibited to the internal memory, however the chip select signal is provided external to the integrated circuit on a pin. The chip select signal may then be used to select an external memory which serves to overlay the internal memory address range. Thus the debug mode allows instruction code and data to reside in the external memory rather than the internal memory while in the debug mode. This facilitates debugging of the code since the contents of the external memory may be examined, for example by an in-circuit emulator, in a less intrusive manner than the contents of the internal memory may be examined. The debug mode may be enabled by asserting a signal upon a predefined pin at the conclusion of reset of the microcontroller. By providing the predefined pin for placing the microcontroller into the debug mode, the microcontroller may be placed into the debug mode for debug purposes without changing the instruction code being executed thereon. Furthermore, the in-circuit emulator need not have knowledge of the internal memory address range.

Abstract translation: 微控制器集成了由其上包括的核可访问的内部存储器。 微控制器内的逻辑电路将内核产生的内存地址与配置寄存器中的值进行比较，指定内部存储器所在的内存地址范围。 如果产生的存储器地址驻留在指定的地址范围内，则逻辑将产生芯片选择信号到内部存储器，以使内核能够访问内部存储器。 集成电路可以配置在调试模式，其中芯片选择信号被禁止到内部存储器，然而芯片选择信号被提供在引脚上的集成电路的外部。 然后可以使用芯片选择信号来选择用于覆盖内部存储器地址范围的外部存储器。 因此，在调试模式下，调试模式允许指令代码和数据驻留在外部存储器而不是内部存储器中。 这有利于代码的调试，因为外部存储器的内容可以例如通过在线仿真器以比内部存储器的内容更少侵入的方式进行检查。 在微控制器复位结束时，通过在预定义的引脚上断言一个信号可以使能调试模式。 通过提供用于将微控制器置于调试模式的预定义引脚，可以将微控制器置于调试模式以进行调试，而不改变在其上执行的指令代码。 此外，在线仿真器不需要了解内部存储器地址范围。