利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

218 条记录 (耗时 0.031 秒)

    Strained silicon MOSFET having reduced leakage and method of its formation
    3.
    发明授权
    Strained silicon MOSFET having reduced leakage and method of its formation 有权
    应变硅MOSFET具有减少的泄漏和其形成方法

    公开(公告)号：US06924182B1

    公开(公告)日：2005-08-02

    申请号：US10642375

    申请日：2003-08-15

    申请人： Qi Xiang ,  Ming Ren Lin ,  Minh V. Ngo ,  Eric N. Paton ,  Haihong Wang

    发明人： Qi Xiang ,  Ming Ren Lin ,  Minh V. Ngo ,  Eric N. Paton ,  Haihong Wang

    IPC分类号： H01L21/762 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/76

    CPC分类号： H01L21/823878 ,  H01L21/76237 ,  H01L21/823807

    摘要： The formation of shallow trench isolations in a strained silicon MOSFET includes performing ion implantation in the strained silicon layer in the regions to be etched to form the trenches of the shallow trench isolations. The dosage of the implanted ions and the energy of implantation are chosen so as to damage the crystal lattice of the strained silicon throughout the thickness of the strained silicon layer in the shallow trench isolation regions to such a degree that the etch rate of the strained silicon in those regions is increased to approximately the same as or greater than the etch rate of the underlying undamaged silicon germanium. Subsequent etching yields trenches with significantly reduced or eliminated undercutting of the silicon germanium relative to the strained silicon. This in turn substantially prevents the formation of fully depleted silicon on insulator regions under the ends of the gate, thus improving the MOSFET leakage current.

    摘要翻译： 应变硅MOSFET中的浅沟槽隔离的形成包括在被蚀刻的区域中的应变硅层中执行离子注入以形成浅沟槽隔离的沟槽。 选择注入离子的剂量和注入能量，以便在浅沟槽隔离区域中的应变硅层的整个厚度上损坏应变硅的晶格，使得应变硅的蚀刻速率 在这些区域中增加到大致等于或大于底层未损坏的硅锗的蚀刻速率。 随后的蚀刻产生相对于应变硅显着减少或消除硅锗底切的沟槽。 这又大大防止了在栅极端部的绝缘体区域上形成完全耗尽的硅，从而改善MOSFET漏电流。

    Method of forming a thick strained silicon layer and semiconductor structures incorporating a thick strained silicon layer
    4.
    发明授权
    Method of forming a thick strained silicon layer and semiconductor structures incorporating a thick strained silicon layer 有权
    形成厚应变硅层的方法和掺入厚应变硅层的半导体结构

    公开(公告)号：US06730576B1

    公开(公告)日：2004-05-04

    申请号：US10335447

    申请日：2002-12-31

    申请人： Haihong Wang ,  Paul R. Besser ,  Jung-Suk Goo ,  Minh V. Ngo ,  Eric N. Paton ,  Qi Xiang

    发明人： Haihong Wang ,  Paul R. Besser ,  Jung-Suk Goo ,  Minh V. Ngo ,  Eric N. Paton ,  Qi Xiang

    IPC分类号： H01L21762

    CPC分类号： H01L29/7833 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/76224 ,  H01L29/1054 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659

    摘要： A strained silicon layer is grown on a layer of silicon germanium and a layer of silicon germanium is grown on the strained silicon in a single continuous in situ deposition process with the strained silicon. Shallow trench isolations are formed in the lower layer of silicon germanium prior to formation of the strained silicon layer. The two silicon germanium layers effectively provide dual substrates at both surfaces of the strained silicon layer that serve to maintain the tensile strain of the strained silicon layer and resist the formation of misfit dislocations that might otherwise result from temperature changes during processing. Consequently the critical thickness of strained silicon that can be grown without significant misfit dislocations during later processing is effectively doubled for a given germanium content of the silicon germanium layers. The formation of shallow trench isolations prior to formation of the strained silicon layer avoids subjecting the strained silicon layer to extreme thermal stresses and further reduces the formation of misfit dislocations.

    摘要翻译： 应变硅层在硅锗层上生长，并且在应变硅上生长硅锗层，并在应变硅中进行单次连续原位沉积工艺。 在形成应变硅层之前，在硅锗的下层形成浅沟槽隔离。 两个硅锗层有效地在应变硅层的两个表面上提供双重衬底，其用于维持应变硅层的拉伸应变，并抵抗由加工过程中的温度变化引起的失配位错的形成。 因此，对于硅锗层的给定锗含量，可以在后续处理期间可以生长而不显着失配位错的应变硅的临界厚度被有效地加倍。 在形成应变硅层之前形成浅沟槽隔离避免使应变硅层受到极端的热应力，并进一步减少失配位错的形成。

    Nickel alloy for SMOS process silicidation
    8.
    发明授权
    Nickel alloy for SMOS process silicidation 有权
    用于SMOS工艺硅化的镍合金

    公开(公告)号：US06797614B1

    公开(公告)日：2004-09-28

    申请号：US10440847

    申请日：2003-05-19

    申请人： Eric N. Paton ,  Paul R. Besser ,  Minh V. Ngo ,  Qi Xiang

    发明人： Eric N. Paton ,  Paul R. Besser ,  Minh V. Ngo ,  Qi Xiang

    IPC分类号： H01L2144

    CPC分类号： H01L29/1054 ,  H01L21/28518 ,  H01L29/665

    摘要： A process of siliciding uses alloys to reduce the adverse affects of germanium on silicide regions. The alloy can include nickel and at least one of vanadium, tantalum, and tungsten. The process can utilize one or two annealing steps. The process allows better silicidation in SMOS devices. The silicided regions can be provided above a silicon/germanium substrate.

    摘要翻译： 硅化过程使用合金来减少锗对硅化物区域的不利影响。 该合金可以包括镍和钒，钽和钨中的至少一种。 该方法可以利用一个或两个退火步骤。 该过程允许在SMOS器件中更好的硅化。 硅化物区域可以设置在硅/锗衬底之上。