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1.发明授权Method for QCRIT measurement in bulk CMOS using a switched capacitor circuit 有权使用开关电容电路的批量CMOS QCRIT测量方法公开(公告)号：US07881135B2
公开(公告)日：2011-02-01
申请号：US11679406
申请日：2007-02-27
IPC分类号： G11C29/00
CPC分类号： G01R31/318594 , G01R31/318597
摘要： A test setup for estimating the critical charge of a circuit under test (CUT) uses a charge injection circuit having a switched capacitor that is selectively connected to a node of the CUT. A voltage measurement circuit measures the voltage at a tap in the charge injection circuit before and after the charge is injected. When the injected charge causes an upset in the logical state of the CUT, the critical charge is calculated as the product of the voltage difference and the known capacitance of the capacitor. In one embodiment, (NMOS drain strike simulation) the amount of charge injected is controlled by a variable pulse width generator gating the switch of the charge injection circuit. In another embodiment (PMOS drain strike simulation) the amount of charge injected is controlled by a variable voltage supply selectively connected to the charge storage node.
摘要翻译： 用于估计被测电路的临界电荷的测试装置（CUT）使用具有选择性地连接到CUT的节点的开关电容器的电荷注入电路。 电压测量电路测量电荷注入前后电荷注入电路中的电压。 当注入的电荷导致CUT的逻辑状态不正常时，临界电荷被计算为电压差和电容器的已知电容的乘积。 在一个实施例中，（NMOS漏极击穿模拟）通过门控电荷注入电路的开关的可变脉冲宽度发生器来控制注入的电荷量。 在另一实施例（PMOS漏极击穿模拟）中，注入的电荷量由选择性地连接到电荷存储节点的可变电压电源来控制。
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2.发明申请Method for Qcrit Measurement in Bulk CMOS Using a Switched Capacitor Circuit 有权使用开关电容电路的批量CMOS中的Qcrit测量方法公开(公告)号：US20100271057A1
公开(公告)日：2010-10-28
申请号：US11679406
申请日：2007-02-27
IPC分类号： G01R31/30
CPC分类号： G01R31/318594 , G01R31/318597
摘要： A test setup for estimating the critical charge of a circuit under test (CUT) uses a charge injection circuit having a switched capacitor that is selectively connected to a node of the CUT. A voltage measurement circuit measures the voltage at a tap in the charge injection circuit before and after the charge is injected. When the injected charge causes an upset in the logical state of the CUT, the critical charge is calculated as the product of the voltage difference and the known capacitance of the capacitor. In one embodiment, (NMOS drain strike simulation) the amount of charge injected is controlled by a variable pulse width generator gating the switch of the charge injection circuit. In another embodiment (PMOS drain strike simulation) the amount of charge injected is controlled by a variable voltage supply selectively connected to the charge storage node.
摘要翻译： 用于估计被测电路的临界电荷的测试装置（CUT）使用具有选择性地连接到CUT的节点的开关电容器的电荷注入电路。 电压测量电路测量电荷注入前后电荷注入电路中的电压。 当注入的电荷导致CUT的逻辑状态不正常时，临界电荷被计算为电压差和电容器的已知电容的乘积。 在一个实施例中，（NMOS漏极击穿模拟）通过门控电荷注入电路的开关的可变脉冲宽度发生器来控制注入的电荷量。 在另一实施例（PMOS漏极击穿模拟）中，注入的电荷量由选择性地连接到电荷存储节点的可变电压电源来控制。
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公开(公告)号：US20080288197A1
公开(公告)日：2008-11-20
申请号：US11750475
申请日：2007-05-18
申请人： Harmander Singh , Alan J. Drake , Fadi H. Gebara , John P. Keane , Jeremy D. Schaub , Robert M. Senger
发明人： Harmander Singh , Alan J. Drake , Fadi H. Gebara , John P. Keane , Jeremy D. Schaub , Robert M. Senger
IPC分类号： G01R29/02
CPC分类号： G01R31/2874 , G01R31/3016
摘要： A method and system for calibration of multi-metric sensitive delay measurement circuits provides for reduction of process-dependent variation in delays and their sensitivities to circuit metrics. A process corner for the delay circuit(s) is determined from at least one delay measurement for which the variation of delay due to process variation is previously characterized. The delay measurement(s) is made at a known temperature(s), power supply voltage(s) and known values of any other environmental metric which the delay circuit is designed to measure. Coefficients for delay versus circuit metrics are then determined from the established process corner, so that computation of circuit metric values from the delay measurements have improved accuracy and reduced variation due to the circuit-to-circuit and/or die-to-die process variation of the delay circuits.
摘要翻译： 用于校准多度量敏感延迟测量电路的方法和系统提供减少延迟中的过程相关变化及其对电路度量的敏感性。 用于延迟电路的处理角由至少一个延迟测量确定，对于该延迟测量，由于过程变化引起的延迟的变化被预先表征。 延迟测量是在已知的温度，电源电压和延迟电路设计测量的任何其他环境度量的已知值进行的。 然后从建立的过程角确定延迟与电路度量的系数，从而延迟测量的电路度量值的计算由于电路到电路和/或管芯到管芯的工艺变化而提高了精度和减小的变化 的延迟电路。
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4.发明申请Correction of Delay-Based Metric Measurements Using Delay Circuits Having Differing Metric Sensitivities 失效使用具有不同公制灵敏度的延迟电路校正基于延迟的公制测量公开(公告)号：US20080288196A1
公开(公告)日：2008-11-20
申请号：US11750385
申请日：2007-05-18
申请人： Harmander Singh , Alan J. Drake , Fadi H. Gebara , John P. Keane , Jeremy D. Schaub , Robert M. Senger
发明人： Harmander Singh , Alan J. Drake , Fadi H. Gebara , John P. Keane , Jeremy D. Schaub , Robert M. Senger
CPC分类号： G01R31/3016
摘要： Correction of delay-based metric measurements using delay circuits having differing metric sensitivities provides improved accuracy for environmental and other circuit metric measurements that used delay lines. A delay line measurement, which may be a one-shot measurement or a ring oscillator frequency measurement is performed either simultaneously or sequentially using at least two delay lines that have differing sensitivities to a particular metric under measurement. A correction circuit or algorithm uses the measured delays or ring oscillator frequencies and corrects at least one of the metric measurements determined from one of the delays or ring oscillator frequencies in conformity with the other delay or ring oscillator frequency. The delays may be inverter chains, with one chain having a higher sensitivity to supply voltage than the other delay chain, with the other delay chain having a higher sensitivity to temperature. Temperature results can then be corrected for supply voltage variation and vice-versa.
摘要翻译： 使用具有不同的度量灵敏度的延迟电路对基于延迟的度量测量进行校正为使用延迟线的环境和其他电路量度测量提供了改进的精度。 可以使用对测量的特定度量具有不同灵敏度的至少两个延迟线来同时或顺序地执行可以是单次测量或环形振荡器频率测量的延迟线测量。 校正电路或算法使用测量的延迟或环形振荡器频率，并根据其他延迟或环形振荡器频率来校正从延迟或环形振荡器频率之一确定的度量测量中的至少一个。 延迟可以是逆变器链，一个链对电源电压的敏感性高于另一个延迟链，另一个延迟链对温度具有较高的灵敏度。 然后可以对电源电压变化校正温度结果，反之亦然。
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5.发明授权Correction of delay-based metric measurements using delay circuits having differing metric sensitivities 失效使用具有不同度量灵敏度的延迟电路校正基于延迟的度量测量公开(公告)号：US07548823B2
公开(公告)日：2009-06-16
申请号：US11750385
申请日：2007-05-18
申请人： Harmander Singh , Alan J. Drake , Fadi H. Gebara , John P. Keane , Jeremy D. Schaub , Robert M. Senger
发明人： Harmander Singh , Alan J. Drake , Fadi H. Gebara , John P. Keane , Jeremy D. Schaub , Robert M. Senger
IPC分类号： G01R29/00
CPC分类号： G01R31/3016
摘要： Correction of delay-based metric measurements using delay circuits having differing metric sensitivities provides improved accuracy for environmental and other circuit metric measurements that used delay lines. A delay line measurement, which may be a one-shot measurement or a ring oscillator frequency measurement is performed either simultaneously or sequentially using at least two delay lines that have differing sensitivities to a particular metric under measurement. A correction circuit or algorithm uses the measured delays or ring oscillator frequencies and corrects at least one of the metric measurements determined from one of the delays or ring oscillator frequencies in conformity with the other delay or ring oscillator frequency. The delays may be inverter chains, with one chain having a higher sensitivity to supply voltage than the other delay chain, with the other delay chain having a higher sensitivity to temperature. Temperature results can then be corrected for supply voltage variation and vice-versa.
摘要翻译： 使用具有不同的度量灵敏度的延迟电路对基于延迟的度量测量进行校正为使用延迟线的环境和其他电路量度测量提供了改进的精度。 可以使用对测量的特定度量具有不同灵敏度的至少两个延迟线来同时或顺序地执行可以是单次测量或环形振荡器频率测量的延迟线测量。 校正电路或算法使用测量的延迟或环形振荡器频率，并根据其他延迟或环形振荡器频率来校正从延迟或环形振荡器频率之一确定的度量测量中的至少一个。 延迟可以是逆变器链，一个链对电源电压的敏感性高于另一个延迟链，另一个延迟链对温度具有较高的灵敏度。 然后可以对电源电压变化校正温度结果，反之亦然。
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公开(公告)号：US20090144006A1
公开(公告)日：2009-06-04
申请号：US12367893
申请日：2009-02-09
申请人： Harmander Singh , Alan J. Drake , Fadi H. Gebara , John P. Keane , Jeremy D. Schaub , Robert M. Senger
发明人： Harmander Singh , Alan J. Drake , Fadi H. Gebara , John P. Keane , Jeremy D. Schaub , Robert M. Senger
IPC分类号： G01R29/00
CPC分类号： G01R31/2874 , G01R31/3016
摘要： A method and system for calibration of multi-metric sensitive delay measurement circuits provides for reduction of process-dependent variation in delays and their sensitivities to circuit metrics. A process corner for the delay circuit(s) is determined from at least one delay measurement for which the variation of delay due to process variation is previously characterized. The delay measurement(s) is made at a known temperature(s), power supply voltage(s) and known values of any other environmental metric which the delay circuit is designed to measure. Coefficients for delay versus circuit metrics are then determined from the established process corner, so that computation of circuit metric values from the delay measurements have improved accuracy and reduced variation due to the circuit-to-circuit and/or die-to-die process variation of the delay circuits.
摘要翻译： 用于校准多度量敏感延迟测量电路的方法和系统提供减少延迟中的过程相关变化及其对电路度量的敏感性。 用于延迟电路的处理角由至少一个延迟测量确定，对于该延迟测量，由于过程变化引起的延迟的变化被预先表征。 延迟测量是在已知的温度，电源电压和延迟电路设计测量的任何其他环境度量的已知值进行的。 然后从建立的过程角确定延迟与电路度量的系数，从而延迟测量的电路度量值的计算由于电路到电路和/或管芯到管芯的工艺变化而提高了精度和减小的变化 的延迟电路。
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公开(公告)号：US07542862B2
公开(公告)日：2009-06-02
申请号：US11750475
申请日：2007-05-18
申请人： Harmander Singh , Alan J. Drake , Fadi H. Gebara , John P. Keane , Jeremy D. Schaub , Robert M. Senger
发明人： Harmander Singh , Alan J. Drake , Fadi H. Gebara , John P. Keane , Jeremy D. Schaub , Robert M. Senger
CPC分类号： G01R31/2874 , G01R31/3016
摘要： A method and system for calibration of multi-metric sensitive delay measurement circuits provides for reduction of process-dependent variation in delays and their sensitivities to circuit metrics. A process corner for the delay circuit(s) is determined from at least one delay measurement for which the variation of delay due to process variation is previously characterized. The delay measurement(s) is made at a known temperature(s), power supply voltage(s) and known values of any other environmental metric which the delay circuit is designed to measure. Coefficients for delay versus circuit metrics are then determined from the established process corner, so that computation of circuit metric values from the delay measurements have improved accuracy and reduced variation due to the circuit-to-circuit and/or die-to-die process variation of the delay circuits.
摘要翻译： 用于校准多度量敏感延迟测量电路的方法和系统提供减少延迟中的过程相关变化及其对电路度量的敏感性。 用于延迟电路的处理角由至少一个延迟测量确定，对于该延迟测量，由于过程变化引起的延迟的变化被预先表征。 延迟测量是在已知的温度，电源电压和延迟电路设计测量的任何其他环境度量的已知值进行的。 然后从建立的过程角确定延迟与电路度量的系数，从而延迟测量的电路度量值的计算由于电路到电路和/或管芯到管芯的工艺变化而提高了精度和减小的变化 的延迟电路。
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公开(公告)号：US08676516B2
公开(公告)日：2014-03-18
申请号：US13524208
申请日：2012-06-15
IPC分类号： G01L3/00
CPC分类号： G01R31/31725 , G01R31/2856
摘要： A method and test circuit provide measurements to accurately characterize threshold voltage changes due to negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI). Both the bias temperature instability recovery profile and/or the bias temperature shifts due to rapid repetitions of stress application can be studied. In order to provide accurate measurements when stresses are applied at intervals on the order of tens of nanoseconds while avoiding unwanted recovery, and/or to achieve recovery profile sampling resolutions in the nanosecond range, multiple delay or ring oscillator frequency measurements are made using a delay line that is formed from delay elements that have delay variation substantially caused only by NBTI or PBTI effects. Devices in the delay elements are stressed, and then the delay line/ring oscillator is operated to measure a threshold voltage change for one or more measurement periods on the order of nanoseconds.
摘要翻译： 一种方法和测试电路提供测量，以准确表征由于负偏压温度不稳定性（NBTI）和正偏压温度不稳定性（PBTI）引起的阈值电压变化。 可以研究由于应力应用的快速重复引起的偏置温度不稳定性恢复曲线和/或偏置温度偏移。 为了提供精确的测量，当应力以几十纳秒的间隔施加，同时避免不必要的恢复时，和/或实现纳秒范围内的恢复曲线采样分辨率，使用延迟进行多个延迟或环形振荡器频率测量 由具有实质上仅由NBTI或PBTI效应引起的延迟变化的延迟元件形成的线。 延迟元件中的器件受到应力，然后延迟线/环形振荡器被操作以测量一个或多个量级的纳秒的一个或多个测量周期的阈值电压变化。
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公开(公告)号：US07667513B2
公开(公告)日：2010-02-23
申请号：US10988454
申请日：2004-11-12
IPC分类号： H03K3/017
CPC分类号： H03K5/1565
摘要： A circuit and method of correcting the duty cycle of digital signals is disclosed. The duty cycle of an input digital signal is measured and compared to a desired duty cycle. The leading edge of the input digital signal is passed to an output. The circuit and method adjust the falling edges at the output to achieve the desired duty cycle. The falling edges occur in response to rising edges of a delayed version of the input digital signal.
摘要翻译： 公开了一种校正数字信号占空比的电路和方法。 测量输入数字信号的占空比并将其与期望的占空比进行比较。 输入数字信号的前沿被传递到输出。 该电路和方法调节输出端的下降沿以达到所需的占空比。 响应于延迟版本的输入数字信号的上升沿发生下降沿。
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10.发明申请Delay-Based Bias Temperature Instability Recovery Measurements for Characterizing Stress Degradation and Recovery 失效基于延迟的偏压温度不稳定性恢复测量，用于表征应力退化和恢复公开(公告)号：US20090319202A1
公开(公告)日：2009-12-24
申请号：US12142294
申请日：2008-06-19
IPC分类号： G01L1/00
CPC分类号： G01R31/31725 , G01R31/2856
摘要： A method, test circuit and test system provide measurements to accurately characterize threshold voltage changes due to negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI). Both the bias temperature instability recovery profile and/or the bias temperature shifts due to rapid repetitions of stress application can be studied. In order to provide accurate measurements when stresses are applied at intervals on the order of tens of nanoseconds while avoiding unwanted recovery, and/or to achieve recovery profile sampling resolutions in the nanosecond range, multiple delay or ring oscillator frequency measurements are made using a delay line that is formed from delay elements that have delay variation substantially caused only by NBTI or PBTI effects. Devices in the delay elements are stressed, and then the delay line/ring oscillator is operated to measure a threshold voltage change for one or more measurement periods on the order of nanoseconds.
摘要翻译： 一种方法，测试电路和测试系统提供测量以精确表征由于负偏压温度不稳定性（NBTI）和正偏压温度不稳定性（PBTI）引起的阈值电压变化。 可以研究由于应力应用的快速重复引起的偏置温度不稳定性恢复曲线和/或偏置温度偏移。 为了提供精确的测量，当应力以几十纳秒的间隔施加，同时避免不必要的恢复时，和/或实现纳秒范围内的恢复曲线采样分辨率，使用延迟进行多个延迟或环形振荡器频率测量 由具有实质上仅由NBTI或PBTI效应引起的延迟变化的延迟元件形成的线。 延迟元件中的器件受到应力，然后延迟线/环形振荡器被操作以测量一个或多个量级的纳秒的一个或多个测量周期的阈值电压变化。
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