公开(公告)号：US20080299421A1

公开(公告)日：2008-12-04

申请号：US12063919

申请日：2005-10-31

申请人： Eun Ae Cho ,  In-Hwan Oh ,  Hyoung-Juhn Kim ,  Yeong Cheon Kim ,  Sang-Yeop Lee ,  Tae-Hoon Lim ,  Suk-woo Nam ,  Sung Pil Yoon ,  Jonghee Han ,  Heung Yong Ha ,  Hyung Chul Hahm ,  Jaeyoung Lee

发明人： Eun Ae Cho ,  In-Hwan Oh ,  Hyoung-Juhn Kim ,  Yeong Cheon Kim ,  Sang-Yeop Lee ,  Tae-Hoon Lim ,  Suk-woo Nam ,  Sung Pil Yoon ,  Jonghee Han ,  Heung Yong Ha ,  Hyung Chul Hahm ,  Jaeyoung Lee

IPC分类号： H01M8/00

CPC分类号： G01N27/40

摘要： A separation plate having a gas flow path is segmented for analyzing MEA performance without segmenting an electrode or a gas diffusion layer. In advance, a MEA is operated for a long time in a real stack environment using a typical separation plate which is not segmented, and then the segmented separation plate for analyzing MEA performance is mounted to the MEA.

摘要翻译： 具有气体流路的分离板被分割以分析MEA性能而不分割电极或气体扩散层。 事先，使用典型的未分段的分离板，在真实堆叠环境中长时间运行MEA，然后将用于分析MEA性能的分段分离板安装到MEA。

公开(公告)号：US20080241620A1

公开(公告)日：2008-10-02

申请号：US11967521

申请日：2007-12-31

申请人： Hyung Chul Ham ,  Seong-Ahn Hong ,  In-Hwan Oh ,  Tae-Hoon Lim ,  Suk Woo Nam ,  Heung Yong Ha ,  Jonghee Han ,  Sung Pil Yoon ,  Jaeyoung Lee ,  Hyoung-Juhn Kim ,  Eun Ae Cho ,  Yeong Cheon Kim ,  Sang-Yeop Lee

发明人： Hyung Chul Ham ,  Seong-Ahn Hong ,  In-Hwan Oh ,  Tae-Hoon Lim ,  Suk Woo Nam ,  Heung Yong Ha ,  Jonghee Han ,  Sung Pil Yoon ,  Jaeyoung Lee ,  Hyoung-Juhn Kim ,  Eun Ae Cho ,  Yeong Cheon Kim ,  Sang-Yeop Lee

IPC分类号： H01M2/14 ,  H01M8/02 ,  H01M8/04

CPC分类号： H01M8/0267 ,  H01M8/0258 ,  H01M8/04014 ,  H01M8/244 ,  H01M2008/147 ,  Y02E60/526

摘要： A separator for cooling an MCFC has a cooling gas flow path provided in the separator, a cooling anode gas or a cooling cathode gas flowing through the cooling gas flow path, the cooling anode gas or the cooling cathode gas having a temperature lower than that of a general anode gas or a general cathode gas which is supplied to an anode or a cathode of the MCFC.

摘要翻译： 用于冷却MCFC的分离器具有设置在分离器中的冷却气体流路，流过冷却气体流路的冷却阳极气体或冷却阴极气体，冷却阳极气体或冷却阴极气体的温度低于 一般的阳极气体或一般的阴极气体供给至MCFC的阳极或阴极。

公开(公告)号：US08293138B2

公开(公告)日：2012-10-23

申请号：US12004274

申请日：2007-12-19

申请人： Hyoung-Juhn Kim ,  Jeung Woo Lee ,  Tae-Hoon Lim ,  Suk Woo Nam ,  Seong-Ahn Hong ,  In-Hwan Oh ,  Hyung Chul Ham ,  Sang-Yeop Lee

发明人： Hyoung-Juhn Kim ,  Jeung Woo Lee ,  Tae-Hoon Lim ,  Suk Woo Nam ,  Seong-Ahn Hong ,  In-Hwan Oh ,  Hyung Chul Ham ,  Sang-Yeop Lee

IPC分类号： H01B1/12 ,  C08G73/06

CPC分类号： C08J5/2256 ,  C08G73/18 ,  C08J2379/04 ,  H01M8/103 ,  H01M8/1048 ,  H01M8/1072 ,  H01M2300/0082 ,  Y02P70/56

摘要： A partially sulfonated polybenzimidazole based polymer for fuel cell membrane is prepared by copolymerizing monomers of 3,3′-diaminobenzidine, isophthalic acid and 5-sulfoisophthalic acid to obtain a partially sulfonated polybenzimidazole, and doping the partially sulfonated polybenzimidazole with inorganic acid.

摘要翻译： 通过共聚3,3'-二氨基联苯胺，间苯二甲酸和5-磺基间苯二甲酸的单体制备用于燃料电池膜的部分磺化的聚苯并咪唑基聚合物，以获得部分磺化的聚苯并咪唑，并用无机酸掺杂部分磺化的聚苯并咪唑。

公开(公告)号：US20080241627A1

公开(公告)日：2008-10-02

申请号：US12004274

申请日：2007-12-19

申请人： Hyoung-Juhn Kim ,  Jeung Woo Lee ,  Tae-Hoon Lim ,  Suk Woo Nam ,  Seong-Ahn Hong ,  In-Hwan Oh ,  Hyung Chul Ham ,  Sang-Yeop Lee

发明人： Hyoung-Juhn Kim ,  Jeung Woo Lee ,  Tae-Hoon Lim ,  Suk Woo Nam ,  Seong-Ahn Hong ,  In-Hwan Oh ,  Hyung Chul Ham ,  Sang-Yeop Lee

IPC分类号： H01M8/10

CPC分类号： C08J5/2256 ,  C08G73/18 ,  C08J2379/04 ,  H01M8/103 ,  H01M8/1048 ,  H01M8/1072 ,  H01M2300/0082 ,  Y02P70/56

摘要： A partially sulfonated polybenzimidazole based polymer for fuel cell membrane is prepared by copolymerizing monomers of 3,3′-diaminobenzidine, isophthalic acid and 5-sulfoisophthalic acid to obtain a partially sulfonated polybenzimidazole, and doping the partially sulfonated polybenzimidazole with inorganic acid.

摘要翻译： 通过共聚3,3'-二氨基联苯胺，间苯二甲酸和5-磺基间苯二甲酸的单体制备用于燃料电池膜的部分磺化的聚苯并咪唑基聚合物，以获得部分磺化的聚苯并咪唑，并用无机酸掺杂部分磺化的聚苯并咪唑。

公开(公告)号：US20050054186A1

公开(公告)日：2005-03-10

申请号：US10885769

申请日：2004-07-08

申请人： Jin-Ho Kim ,  In-Ku Kang ,  Sang-Yeop Lee

发明人： Jin-Ho Kim ,  In-Ku Kang ,  Sang-Yeop Lee

IPC分类号： H01L21/60 ,  H01L21/44 ,  H01L21/607

CPC分类号： H01L24/85 ,  H01L24/45 ,  H01L24/48 ,  H01L24/78 ,  H01L2224/02126 ,  H01L2224/02166 ,  H01L2224/05554 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4809 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48472 ,  H01L2224/48479 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/78301 ,  H01L2224/85045 ,  H01L2224/85051 ,  H01L2224/85181 ,  H01L2224/85205 ,  H01L2224/85951 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2224/4554 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A method of wire bonding, a semiconductor chip, and a semiconductor package provides stitch-stitch bonds of a wire on a bond pad of a chip as well as on a bond position of a substrate. A ball-stitch bump is formed on an end of the wire extending from a capillary or provided on the bond pad of the chip. A ball-stitch bump is formed on the bond pad of the chip by pressing down the ball of the wire on the bond pad. A ball-stitch stitch bond of the wire is formed on the ball-stitch bump by pressing down the wire on the ball-stitch bump. The capillary is moved from the bond pad to the bond position, while loosening the wire. A stitch bond of the wire is formed on the bond position by pressing down the wire on the bond position, and then separated from the wire within the capillary. The method of wire bonding, a semiconductor chip, and a semiconductor package can reduce or minimize a moving path of the capillary and provide more effective wire bonding.

摘要翻译： 引线键合，半导体芯片和半导体封装的方法在芯片的焊盘和基板的接合位置上提供线的针脚结合。 在从毛细管延伸或设置在芯片的接合焊盘上的导线的端部上形成球形针迹。 通过在接合焊盘上压下导线的球，在芯片的接合焊盘上形成球针凸点。 通过按压球形针凸块上的线，在球形针迹上形成线迹的针迹缝合。 毛细管从接合垫移动到接合位置，同时松开电线。 通过在接合位置压下导线，在接合位置形成线的针脚接合，然后与毛细管内的线分离。 引线键合，半导体芯片和半导体封装的方法可以减少或最小化毛细管的移动路径并提供更有效的引线键合。

公开(公告)号：US20050023674A1

公开(公告)日：2005-02-03

申请号：US10632700

申请日：2003-07-31

申请人： In-Ku Kang ,  Hee-Kook Choi ,  Sang-Ho An ,  Sang-Yeop Lee

发明人： In-Ku Kang ,  Hee-Kook Choi ,  Sang-Ho An ,  Sang-Yeop Lee

IPC分类号： H01L25/065 ,  H01L23/34

CPC分类号： H01L24/48 ,  H01L24/45 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48471 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

摘要： Provided herein are multi-chip modules (MCMs) having bonding wires and fabrication methods thereof. The multi-chip module includes a substrate and a plurality of chips sequentially stacked. At least one top chip, stacked above a lowest chip, has an insulating film that covers the backside thereof. Also, each of the stacked chips has bonding pads formed on the periphery or edges of its upper surface. At least one insulator is interposed between the stacked chips. The insulator exposes the pads on the underlying chip. The pads of the respective chips are connected to a set of interconnections, which are disposed on the substrate. This configuration of stacked chips enables the overall height of the memory module to be reduced because the insulating film prevents the bonding wires from contacting the substrate of the top chips.

摘要翻译： 本文提供具有接合线的多芯片模块（MCM）及其制造方法。 多芯片模块包括基板和顺序层叠的多个芯片。 堆叠在最低芯片上方的至少一个顶部芯片具有覆盖其背面的绝缘膜。 此外，每个堆叠的芯片具有形成在其上表面的周边或边缘上的接合焊盘。 在堆叠的芯片之间插入至少一个绝缘体。 绝缘体暴露底层芯片上的焊盘。 各个芯片的焊盘连接到一组布置在基板上的互连。 堆叠式芯片的这种配置使得由于绝缘膜防止接合线接触顶部芯片的基板而使存储器模块的整体高度减小。

公开(公告)号：US07410832B2

公开(公告)日：2008-08-12

申请号：US11727298

申请日：2007-03-26

申请人： Sang-Yeop Lee ,  Min-Il Kim

发明人： Sang-Yeop Lee ,  Min-Il Kim

IPC分类号： H01L21/48 ,  H01L21/50

CPC分类号： H01L25/0657 ,  H01L24/48 ,  H01L24/73 ,  H01L24/92 ,  H01L25/50 ,  H01L2224/05599 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/4899 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2224/85909 ,  H01L2224/8592 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2225/06586 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K13/0469 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

摘要： The invention provides a semiconductor chip package, and a means of forming such a semiconductor chip package, in which one or more semiconductor chips are electrically connected to a mounting substrate by wire bonding in which an adhesive tape is provided on the active surface of the semiconductor chips for encapsulating at least an upper portion of the bonding wires adjacent the active surfaces to improve the stability of the bonding wires during subsequent processing.

摘要翻译： 本发明提供一种半导体芯片封装以及形成这样的半导体芯片封装的方法，其中一个或多个半导体芯片通过引线接合电连接到安装基板，其中胶带设置在半导体的有源表面上 芯片，用于至少封装接合线的上部与邻近的活性表面，以提高接合线的后续处理过程中的稳定性。

公开(公告)号：US20080086858A1

公开(公告)日：2008-04-17

申请号：US11987844

申请日：2007-12-05

申请人： Sang-Yeop Lee ,  Cheul-Joong Youn

发明人： Sang-Yeop Lee ,  Cheul-Joong Youn

IPC分类号： H01L21/67

CPC分类号： H01L21/67092 ,  H01L21/6836 ,  H01L21/78 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  Y10T29/41

摘要： A method and apparatus of fabricating a semiconductor device by back grinding and dicing is disclosed. The method may include at least adhering a protection tape for back grinding on a front surface of a semiconductor wafer, back grinding a rear surface of the semiconductor wafer while the protection tape faces downward, loading the semiconductor wafer to dicing equipment when the front surface having the protection tape faces downward, detecting a dicing position formed on the front surface of the semiconductor wafer, and dicing the semiconductor wafer with the protection tape adhering thereon into individual semiconductor chips in accordance with the detected dicing position. The dicing equipment may have a transparent aligning part for aligning the semiconductor wafer and a chuck part for supporting the semiconductor wafer.

公开(公告)号：US20050196939A1

公开(公告)日：2005-09-08

申请号：US10984843

申请日：2004-11-10

申请人： Sang-Yeop Lee ,  Cheul-Joong Youn

发明人： Sang-Yeop Lee ,  Cheul-Joong Youn

IPC分类号： H01L21/78 ,  H01L21/301 ,  H01L21/44 ,  H01L21/46 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L21/67092 ,  H01L21/6836 ,  H01L21/78 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  Y10T29/41

摘要： A method and apparatus of fabricating a semiconductor device by back grinding and dicing is disclosed. The method may include at least adhering a protection tape for back grinding on a front surface of a semiconductor wafer, back grinding a rear surface of the semiconductor wafer while the protection tape faces downward, loading the semiconductor wafer to dicing equipment when the front surface having the protection tape faces downward, detecting a dicing position formed on the front surface of the semiconductor wafer, and dicing the semiconductor wafer with the protection tape adhering thereon into individual semiconductor chips in accordance with the detected dicing position. The dicing equipment may have a transparent aligning part for aligning the semiconductor wafer and a chuck part for supporting the semiconductor wafer.

摘要翻译： 公开了一种通过背面研磨和切割制造半导体器件的方法和装置。 该方法可以包括至少在半导体晶片的前表面上粘贴用于背面研磨的保护带，当保护带朝下时，背面研磨半导体晶片的后表面，当前表面具有 保护带面向下，检测形成在半导体晶片的前表面上的切割位置，并根据检测到的切割位置将其上粘附有保护带的半导体晶片切割成单独的半导体芯片。 切割设备可以具有用于对准半导体晶片的透明对准部分和用于支撑半导体晶片的卡盘部分。

公开(公告)号：US20070029650A1

公开(公告)日：2007-02-08

申请号：US11361729

申请日：2006-02-23

申请人： Won-Chul Lim ,  Sang-Yeop Lee

发明人： Won-Chul Lim ,  Sang-Yeop Lee

IPC分类号： H01L23/495

CPC分类号： H01L23/49555 ,  H01L25/105 ,  H01L25/50 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor package presents Z-shaped outer leads. The outer leads have a first portion located near an upper surface of a package body, a second portion, and a third portion located near a lower surface of a package body. A second similar semiconductor package may be stacked on the first semiconductor package with the third portion of the second semiconductor package located on and electrically connected to the first portion of the first semiconductor package. In each of the first and second semiconductor packages, a distance between the bottom surface of the third portion of the outer lead and the lower surface of a package body may be greater than a distance between the top surface of the first portion of the outer lead and the upper surface of the package body.

摘要翻译： 半导体封装呈现Z形外引线。 外引线具有位于封装主体的上表面附近的第一部分，第二部分和位于封装主体的下表面附近的第三部分。 第二类似的半导体封装可以堆叠在第一半导体封装上，其中第二半导体封装的第三部分位于第一半导体封装的第一部分上，并且与第一半导体封装的第一部分电连接。 在第一和第二半导体封装的每一个中，外部引线的第三部分的底表面和封装主体的下表面之间的距离可以大于外引线的第一部分的顶表面之间的距离 和包装体的上表面。