公开(公告)号：US20080001209A1

公开(公告)日：2008-01-03

申请号：US11783548

申请日：2007-04-10

申请人： Eun-Suk Cho ,  Kyu-Charn Park ,  Jong-Jin Lee ,  Jeong-Dong Choe

发明人： Eun-Suk Cho ,  Kyu-Charn Park ,  Jong-Jin Lee ,  Jeong-Dong Choe

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/7883 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/42336

摘要： A non-volatile memory device may include a substrate having a field region and an active region including a rounded upper edge portion and a flat upper central portion, an effective tunnel oxide layer on the flat upper central portion of the active region, a split floating gate electrode on the effective tunnel oxide layer, the floating gate electrode having a width greater than a width of the effective tunnel oxide layer, a dielectric layer pattern on the floating gate electrode, the dielectric layer pattern including metal oxide, and a control gate electrode on the dielectric layer pattern.

摘要翻译： 非易失性存储器件可以包括具有场区域和包括圆形上边缘部分和平坦上中心部分的有源区域的基板，在有源区域的平坦上中心部分上的有效隧道氧化物层，分裂浮动 栅极电极在有效隧道氧化物层上，浮栅电极的宽度大于有效隧道氧化物层的宽度，浮栅电极上的电介质层图案，包括金属氧化物的电介质层图案和控制栅电极 在电介质层图案上。

公开(公告)号：US08049269B2

公开(公告)日：2011-11-01

申请号：US11898266

申请日：2007-09-11

申请人： Se-Hoon Lee ,  Kyu-Charn Park ,  Jeong-Dong Choe

发明人： Se-Hoon Lee ,  Kyu-Charn Park ,  Jeong-Dong Choe

IPC分类号： H01L29/792 ,  H01L29/788 ,  H01L21/336 ,  H01L21/8247

CPC分类号： H01L27/115 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

摘要： In a non-volatile memory device, active fin structures extending in a first direction may be formed on a substrate. A tunnel insulating layer may be formed on surfaces of the active fin structures and bottom surfaces of trenches that may be defined by the active fin structures. A charge trapping layer and a blocking layer may be sequentially formed on the tunnel insulating layer. A gate electrode structure may include first portions disposed over top surfaces of the active fin structures and second portions vertically spaced apart from portions of the charge trapping layer that may be disposed over the bottom surfaces of the trenches, and may extend in a second direction substantially perpendicular to the first direction. Thus, lateral electron diffusion may be reduced in the charge trapping layer, and thereby the data retention performance and/or reliability of the non-volatile memory device may be improved.

摘要翻译： 在非易失性存储器件中，可以在衬底上形成沿第一方向延伸的活性鳍结构。 隧道绝缘层可以形成在活动鳍结构和沟槽底表面的表面上，沟槽绝缘层可以由活性鳍结构限定。 电荷俘获层和阻挡层可以顺序形成在隧道绝缘层上。 栅极电极结构可以包括设置在有源鳍结构的顶表面上的第一部分和与可以设置在沟槽的底表面之上的电荷俘获层的部分垂直间隔开的第二部分，并且可以在基本上 垂直于第一方向。 因此，电荷捕捉层中的横向电子扩散可能减少，从而可以提高非易失性存储器件的数据保持性能和/或可靠性。

公开(公告)号：US20080061361A1

公开(公告)日：2008-03-13

申请号：US11898266

申请日：2007-09-11

申请人： Se-Hoon Lee ,  Kyu-Charn Park ,  Jeong-Dong Choe

发明人： Se-Hoon Lee ,  Kyu-Charn Park ,  Jeong-Dong Choe

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

摘要： In a non-volatile memory device, active fin structures extending in a first direction may be formed on a substrate. A tunnel insulating layer may be formed on surfaces of the active fin structures and bottom surfaces of trenches that may be defined by the active fin structures. A charge trapping layer and a blocking layer may be sequentially formed on the tunnel insulating layer. A gate electrode structure may include first portions disposed over top surfaces of the active fin structures and second portions vertically spaced apart from portions of the charge trapping layer that may be disposed over the bottom surfaces of the trenches, and may extend in a second direction substantially perpendicular to the first direction. Thus, lateral electron diffusion may be reduced in the charge trapping layer, and thereby the data retention performance and/or reliability of the non-volatile memory device may be improved.

摘要翻译： 在非易失性存储器件中，可以在衬底上形成沿第一方向延伸的活性鳍结构。 隧道绝缘层可以形成在活动鳍结构和沟槽底表面的表面上，沟槽绝缘层可以由活性鳍结构限定。 电荷俘获层和阻挡层可以顺序形成在隧道绝缘层上。 栅极电极结构可以包括设置在有源鳍结构的顶表面上的第一部分和与可以设置在沟槽的底表面之上的电荷俘获层的部分垂直间隔开的第二部分，并且可以在基本上 垂直于第一方向。 因此，电荷捕捉层中的横向电子扩散可能减少，从而可以提高非易失性存储器件的数据保持性能和/或可靠性。

公开(公告)号：US07449763B2

公开(公告)日：2008-11-11

申请号：US11530827

申请日：2006-09-11

申请人： Chang-Hyun Lee ,  Kyu-Charn Park ,  Jeong-Hyuk Choi ,  Sung-Hoi Hur

发明人： Chang-Hyun Lee ,  Kyu-Charn Park ,  Jeong-Hyuk Choi ,  Sung-Hoi Hur

IPC分类号： H01L29/00 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11519 ,  Y10S257/905

摘要： This disclosure provides cells of nonvolatile memory devices with floating gates and methods for fabricating the same. The cell of the nonvolatile memory device includes device isolation layers in parallel with each other on a predetermined region of a semiconductor substrate that define a plurality of active regions. Each device isolation layer has sidewalls that project over the semiconductor substrate. A plurality of word lines crosses over the device isolation layers. A tunnel oxide layer, a floating gate, a gate interlayer dielectric layer, and a control gate electrode are sequentially stacked between each active region and each word line. The floating gate and the control gate electrode have sidewalls that are self-aligned to the adjacent device isolation layers. The method for forming the self-aligned floating gate and the control gate electrode includes forming trenches in a semiconductor substrate to define a plurality of active regions and concurrently forming an oxide layer pattern, a floating gate pattern, a dielectric layer pattern and a control gate pattern that are sequentially stacked. A conductive layer is then formed on the device isolation layers and the control gate pattern. Thereafter, the conductive layer, the control gate pattern, the dielectric layer pattern, the floating gate pattern, and the oxide layer pattern are successively patterned.

摘要翻译： 本公开提供具有浮动栅极的非易失性存储器件单元以及用于制造其的方法。 非易失性存储器件的单元包括在限定多个有源区域的半导体衬底的预定区域上彼此并联的器件隔离层。 每个器件隔离层具有突出在半导体衬底上的侧壁。 多个字线跨越器件隔离层。 隧道氧化物层，浮置栅极，栅极层间电介质层和控制栅极电极顺序堆叠在每个有源区域和每条字线之间。 浮栅和控制栅极具有与相邻器件隔离层自对准的侧壁。 形成自对准浮栅和控制栅极的方法包括在半导体衬底中形成沟槽以限定多个有源区并同时形成氧化物层图案，浮栅图案，电介质层图案和控制栅极 顺序堆叠的图案。 然后在器件隔离层和控制栅极图案上形成导电层。 此后，连续地形成导电层，控制栅极图案，电介质层图案，浮栅图案和氧化物层图案。

公开(公告)号：US20080203377A1

公开(公告)日：2008-08-28

申请号：US12035169

申请日：2008-02-21

申请人： Byung-Yong Choi ,  Choong-Ho Lee ,  Kyu-Charn Park

发明人： Byung-Yong Choi ,  Choong-Ho Lee ,  Kyu-Charn Park

IPC分类号： H01L47/00

CPC分类号： H01L45/165 ,  H01L27/2436 ,  H01L45/085 ,  H01L45/1206 ,  H01L45/1226 ,  H01L45/146

摘要： Integrated circuit nonvolatile memory devices are manufactured by forming a variable resistance layer on an integrated circuit substrate. The variable resistance layer includes grains that define grain boundaries between the grains. Conductive filaments are formed along at least some of the grain boundaries. Electrodes are formed on the variable resistance layer. The conductive filaments may be formed by implanting conductive ions into at least some of the grain boundaries. Moreover, the variable resistance layer may be a variable resistance oxide of a metal, and the conductive filaments may be the metal. Related devices are also disclosed.

摘要翻译： 通过在集成电路基板上形成可变电阻层来制造集成电路非易失性存储器件。 可变电阻层包括限定晶粒之间的晶界的晶粒。 沿着至少一些晶界形成导电丝。 电极形成在可变电阻层上。 可以通过将导电离子注入至少一些晶界来形成导电细丝。 此外，可变电阻层可以是金属的可变电阻氧化物，并且导电丝可以是金属。 还公开了相关设备。

公开(公告)号：US20080081411A1

公开(公告)日：2008-04-03

申请号：US11616582

申请日：2006-12-27

申请人： Hye-Jin Cho ,  Kyu-Charn Park ,  Choong-Ho Lee ,  Byung-Yong Choi

发明人： Hye-Jin Cho ,  Kyu-Charn Park ,  Choong-Ho Lee ,  Byung-Yong Choi

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： In a method of manufacturing a non-volatile memory device, a conductive structure is formed on a substrate. The conductive structure includes a tunnel oxide pattern, a first conductive pattern, a pad oxide pattern and a hard mask pattern. A trench is formed on the substrate using the conductive structure as an etching mask. An inner oxide layer is formed on an inner wall of the trench and sidewalls of the tunnel oxide pattern and the first conductive pattern. The inner oxide layer is cured, thereby forming a silicon nitride layer on the inner oxide layer. A device isolation pattern is formed in the trench, and the hard mask pattern and the pad oxide pattern are removed from the substrate. A dielectric layer and a second conductive pattern are formed on the substrate. Accordingly, the silicon nitride layer prevents-hydrogen (H) atoms from leaking into the device isolation pattern.

摘要翻译： 在制造非易失性存储器件的方法中，在衬底上形成导电结构。 导电结构包括隧道氧化物图案，第一导电图案，衬垫氧化物图案和硬掩模图案。 使用导电结构作为蚀刻掩模在衬底上形成沟槽。 在沟槽的内壁和隧道氧化物图案的侧壁和第一导电图案上形成内部氧化物层。 内部氧化物层被固化，从而在内部氧化物层上形成氮化硅层。 在沟槽中形成器件隔离图案，并且从衬底去除硬掩模图案和衬垫氧化物图案。 在基板上形成电介质层和第二导电图案。 因此，氮化硅层防止氢（H）原子泄漏到器件隔离图案中。

公开(公告)号：US06737335B2

公开(公告)日：2004-05-18

申请号：US10440806

申请日：2003-05-19

申请人： Jung-Dal Choi ,  Kyu-Charn Park ,  Dong-Seog Eun

发明人： Jung-Dal Choi ,  Kyu-Charn Park ,  Dong-Seog Eun

IPC分类号： H01L2176

CPC分类号： H01L27/11526 ,  H01L21/76229 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/105 ,  H01L27/11541 ,  Y10S438/981

摘要： A shallow trench isolation type semiconductor device includes a gate insulating layer formed in a first region and in a second region. The gate insulating layer is of greater thickness in the first region, relative to the thickness of the gate insulating layer in the second region. A shallow trench isolation layer is also formed in the first region and the second region, the shallow trench isolation layer in the first region being thinner than shallow trench isolation layer in the second region.

摘要翻译： 浅沟槽隔离型半导体器件包括在第一区域和第二区域中形成的栅极绝缘层。 栅极绝缘层相对于第二区域中的栅极绝缘层的厚度在第一区域中具有更大的厚度。 在第一区域和第二区域中还形成浅沟槽隔离层，第一区域中的浅沟槽隔离层比第二区域中的浅沟槽隔离层更薄。

公开(公告)号：US06515329B2

公开(公告)日：2003-02-04

申请号：US10068483

申请日：2002-02-05

申请人： Won-Hong Lee ,  Sung-Nam Chang ,  Kyu-Charn Park

发明人： Won-Hong Lee ,  Sung-Nam Chang ,  Kyu-Charn Park

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11524

摘要： Provided are a non-volatile flash memory device and a method of making the non-volatile flash memory device. A common source line is formed simultaneously with the formation of stacked transistors. The common source line is formed of the same material layer as floating gate pattern. The common source region and a scribe line region are simultaneously formed thorough the same photolithography process in a semiconductor substrate. Additionally, the common source line and butted contact are patterned simultaneously through the same photolithography process. Accordingly, the common source line process can be advantageously completed with very low cost and simplicity.

公开(公告)号：US06376876B1

公开(公告)日：2002-04-23

申请号：US09678917

申请日：2000-10-04

申请人： Kwang-Shik Shin ,  Kyu-Charn Park ,  Heung-Kwun Oh ,  Sung-Hoi Hur

发明人： Kwang-Shik Shin ,  Kyu-Charn Park ,  Heung-Kwun Oh ,  Sung-Hoi Hur

IPC分类号： H01L2978

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： NAND-type flash memory devices and methods of fabricating the same are provided. The NAND-type flash memory device includes a plurality of isolation layers running parallel with each other, which are formed at predetermined regions of a semiconductor substrate. This device also includes a string selection line pattern, a plurality of word line patterns and a ground selection line pattern which cross over the isolation layers and active regions between the isolation layers. Source regions are formed in the active regions adjacent to the ground selection line patterns and opposite the string selection line pattern. The source regions and the isolation layers between the source regions are covered with a common source line running parallel with the ground selection line pattern.

摘要翻译： 提供了NAND​​型闪存器件及其制造方法。 NAND型闪速存储器件包括彼此平行延伸的多个隔离层，它们形成在半导体衬底的预定区域。 该装置还包括串联选择线图案，多个字线图案和跨越隔离层和隔离层之间的有源区域的接地选择线图案。 源极区域形成在与地选择线图案相邻的有源区域中并且与串选择线图案相反。 源极区域和源极区域之间的隔离层被与地选择线图案平行延伸的公共源极线覆盖。

公开(公告)号：US20090253243A1

公开(公告)日：2009-10-08

申请号：US12485577

申请日：2009-06-16

申请人： Hye-Jin Cho ,  Kyu-Charn Park ,  Choong-Ho Lee ,  Byung-Yong Choi

发明人： Hye-Jin Cho ,  Kyu-Charn Park ,  Choong-Ho Lee ,  Byung-Yong Choi

IPC分类号： H01L21/762

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： In a method of manufacturing a non-volatile memory device, a conductive structure is formed on a substrate. The conductive structure includes a tunnel oxide pattern, a first conductive pattern, a pad oxide pattern and a hard mask pattern. A trench is formed on the substrate using the conductive structure as an etching mask. An inner oxide layer is formed on an inner wall of the trench and sidewalls of the tunnel oxide pattern and the first conductive pattern. The inner oxide layer is cured, thereby forming a silicon nitride layer on the inner oxide layer. A device isolation pattern is formed in the trench, and the hard mask pattern and the pad oxide pattern are removed from the substrate. A dielectric layer and a second conductive pattern are formed on the substrate. Accordingly, the silicon nitride layer prevents hydrogen (H) atoms from leaking into the device isolation pattern.

摘要翻译： 在制造非易失性存储器件的方法中，在衬底上形成导电结构。 导电结构包括隧道氧化物图案，第一导电图案，衬垫氧化物图案和硬掩模图案。 使用导电结构作为蚀刻掩模在衬底上形成沟槽。 在沟槽的内壁和隧道氧化物图案的侧壁和第一导电图案上形成内部氧化物层。 内部氧化物层被固化，从而在内部氧化物层上形成氮化硅层。 在沟槽中形成器件隔离图案，并且从衬底去除硬掩模图案和衬垫氧化物图案。 在基板上形成电介质层和第二导电图案。 因此，氮化硅层防止氢（H）原子泄漏到器件隔离图案中。