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1.发明申请HIGH MEMORY DENSITY, HIGH INPUT/OUTPUT BANDWIDTH LOGIC-MEMORY STRUCTURE AND ARCHITECTURE 有权高内存密度，高输入/输出带宽逻辑内存结构和架构公开(公告)号：US20120233510A1
公开(公告)日：2012-09-13
申请号：US13043749
申请日：2011-03-09
CPC分类号： G11C5/025 , G11C5/063 , H01L2924/0002 , H01L2924/00
摘要： A chip stack structure includes a logic chip having an active device surface, and memory slices of a memory unit vertically aligned such that a surface of the memory slices is oriented perpendicular to the active device surface of the logic chip. The chip stack structure also includes wiring patterned on an upper surface of the memory slices, the wiring electrically connecting memory leads of the memory slices to logic grids corresponding to logic grid connections of the logic chip.
摘要翻译： 芯片堆叠结构包括具有有源器件表面的逻辑芯片和垂直对齐的存储器单元的存储器片，使得存储器片的表面垂直于逻辑芯片的有源器件表面定向。 芯片堆叠结构还包括在存储器片的上表面上图案化的布线，布线将存储器片的存储器引线电连接到对应于逻辑芯片的逻辑电路连接的逻辑栅极。
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公开(公告)号：US20140024146A1
公开(公告)日：2014-01-23
申请号：US13565848
申请日：2012-08-03
申请人： Diego Anzola , Evan G. Colgan , Kevin K. Dezfulian , Daniel C. Edelstein , Mark C. H. Lamorey , Sampath Purushothaman , Thomas M. Shaw , Roy R. Yu
发明人： Diego Anzola , Evan G. Colgan , Kevin K. Dezfulian , Daniel C. Edelstein , Mark C. H. Lamorey , Sampath Purushothaman , Thomas M. Shaw , Roy R. Yu
IPC分类号： H01L21/768 , H01L21/50 , H01L21/66
CPC分类号： H01L23/585 , H01L23/562 , H01L25/0657 , H01L2224/04042 , H01L2224/05624 , H01L2225/06551 , H01L2225/06565
摘要： A semiconductor structure is provided and includes a substrate having an edge surface and a device surface with a central area, a crack stop structure disposed on the device surface and a circuit structure including components disposed on the device surface in the central area and interconnects electrically coupled to the components. The interconnects are configured to extend from the central area to the edge surface while bridging over the crack stop structure.
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3.发明授权High memory density, high input/output bandwidth logic-memory structure and architecture 有权高内存密度，高输入/输出带宽逻辑内存结构和架构公开(公告)号：US08569874B2
公开(公告)日：2013-10-29
申请号：US13043749
申请日：2011-03-09
CPC分类号： G11C5/025 , G11C5/063 , H01L2924/0002 , H01L2924/00
摘要： A chip stack structure includes a logic chip having an active device surface, and memory slices of a memory unit vertically aligned such that a surface of the memory slices is oriented perpendicular to the active device surface of the logic chip. The chip stack structure also includes wiring patterned on an upper surface of the memory slices, the wiring electrically connecting memory leads of the memory slices to logic grids corresponding to logic grid connections of the logic chip.
摘要翻译： 芯片堆叠结构包括具有有源器件表面的逻辑芯片和垂直对齐的存储器单元的存储器片，使得存储器片的表面垂直于逻辑芯片的有源器件表面定向。 芯片堆叠结构还包括在存储器片的上表面上图案化的布线，布线将存储器片的存储器引线电连接到对应于逻辑芯片的逻辑电路连接的逻辑栅极。
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4.发明授权Processes for enhanced 3D integration and structures generated using the same 有权用于增强3D集成和使用该集成生成的结构的过程公开(公告)号：US08330262B2
公开(公告)日：2012-12-11
申请号：US12698529
申请日：2010-02-02
申请人： Evan G. Colgan , Sampath Purushothaman , Roy R. Yu
发明人： Evan G. Colgan , Sampath Purushothaman , Roy R. Yu
IPC分类号： H01L23/02
CPC分类号： H01L23/49816 , B23P11/00 , H01L21/78 , H01L2924/0002 , H05K1/11 , H05K1/14 , H05K7/00 , Y10T29/49826 , H01L2924/00
摘要： An enhanced 3D integration structure comprises a logic microprocessor chip bonded to a collection of vertically stacked memory slices and an optional set of outer vertical slices comprising optoelectronic devices. Such a device enables both high memory content in close proximity to the logic circuits and a high bandwidth for logic to memory communication. Additionally, the provision of optoelectronic devices in the outer slices of the vertical slice stack enables high bandwidth direct communication between logic processor chips on adjacent enhanced 3D modules mounted next to each other or on adjacent packaging substrates. A method to fabricate such structures comprises using a template assembly which enables wafer format processing of vertical slice stacks.
摘要翻译： 增强的3D集成结构包括结合到垂直堆叠的存储器片的集合的逻辑微处理器芯片和包括光电子器件的可选的一组外部垂直片。 这样一种装置使得能够靠近逻辑电路的高存储器内容和用于逻辑到存储器通信的高带宽。 此外，在垂直切片堆叠的外切片中提供光电子器件可实现彼此相邻或相邻封装衬底上安装的相邻增强3D模块之间的逻辑处理器芯片之间的高带宽直接通信。 制造这种结构的方法包括使用能够对垂直切片堆叠进行晶片格式处理的模板组件。
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5.发明申请Processes for Enhanced 3D Integration and Structures Generated Using the Same 有权用于增强3D集成和使用其生成的结构的过程公开(公告)号：US20110188209A1
公开(公告)日：2011-08-04
申请号：US12698529
申请日：2010-02-02
申请人： Evan G. Colgan , Sampath Purushothaman , Roy R. Yu
发明人： Evan G. Colgan , Sampath Purushothaman , Roy R. Yu
CPC分类号： H01L23/49816 , B23P11/00 , H01L21/78 , H01L2924/0002 , H05K1/11 , H05K1/14 , H05K7/00 , Y10T29/49826 , H01L2924/00
摘要： An enhanced 3D integration structure comprises a logic microprocessor chip bonded to a collection of vertically stacked memory slices and an optional set of outer vertical slices comprising optoelectronic devices. Such a device enables both high memory content in close proximity to the logic circuits and a high bandwidth for logic to memory communication. Additionally, the provision of optoelectronic devices in the outer slices of the vertical slice stack enables high bandwidth direct communication between logic processor chips on adjacent enhanced 3D modules mounted next to each other or on adjacent packaging substrates. A method to fabricate such structures comprises using a template assembly which enables wafer format processing of vertical slice stacks.
摘要翻译： 增强的3D集成结构包括结合到垂直堆叠的存储器片的集合的逻辑微处理器芯片和包括光电子器件的可选的一组外部垂直片。 这样一种装置使得能够靠近逻辑电路的高存储器内容和用于逻辑到存储器通信的高带宽。 此外，在垂直切片堆叠的外切片中提供光电子器件可实现彼此相邻或相邻封装衬底上安装的相邻增强型3D模块之间的逻辑处理器芯片之间的高带宽直接通信。 制造这种结构的方法包括使用能够对垂直切片堆叠进行晶片格式处理的模板组件。
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公开(公告)号：US20140021616A1
公开(公告)日：2014-01-23
申请号：US13553559
申请日：2012-07-19
申请人： Diego Anzola , Evan G. Colgan , Kevin K. Dezfulian , Daniel C. Edelstein , Mark C. H. Lamorey , Sampath Purushothaman , Thomas M. Shaw , Roy R. Yu
发明人： Diego Anzola , Evan G. Colgan , Kevin K. Dezfulian , Daniel C. Edelstein , Mark C. H. Lamorey , Sampath Purushothaman , Thomas M. Shaw , Roy R. Yu
IPC分类号： H01L23/532 , H01L23/58
CPC分类号： H01L23/585 , H01L23/562 , H01L25/0657 , H01L2224/04042 , H01L2224/05624 , H01L2225/06551 , H01L2225/06565
摘要： A semiconductor structure is provided and includes a substrate having an edge surface and a device surface with a central area, a crack stop structure disposed on the device surface and a circuit structure including components disposed on the device surface in the central area and interconnects electrically coupled to the components. The interconnects are configured to extend from the central area to the edge surface while bridging over the crack stop structure.
摘要翻译： 提供半导体结构，并且包括具有边缘表面的基底和具有中心区域的器件表面，设置在器件表面上的裂纹阻挡结构以及包括设置在中心区域的器件表面上的部件的电路结构，并将电耦合 到组件。 互连构造成在桥接在裂纹停止结构上的同时从中心区域延伸到边缘表面。
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公开(公告)号：US08476753B2
公开(公告)日：2013-07-02
申请号：US13586054
申请日：2012-08-15
申请人： Evan G. Colgan , Sampath Purushothaman , Roy R. Yu
发明人： Evan G. Colgan , Sampath Purushothaman , Roy R. Yu
IPC分类号： H01L23/02
CPC分类号： H01L23/49816 , B23P11/00 , H01L21/78 , H01L2924/0002 , H05K1/11 , H05K1/14 , H05K7/00 , Y10T29/49826 , H01L2924/00
摘要： An enhanced 3D integration structure comprises a logic microprocessor chip bonded to a collection of vertically stacked memory slices and an optional set of outer vertical slices comprising optoelectronic devices. Such a device enables both high memory content in close proximity to the logic circuits and a high bandwidth for logic to memory communication. Additionally, the provision of optoelectronic devices in the outer slices of the vertical slice stack enables high bandwidth direct communication between logic processor chips on adjacent enhanced 3D modules mounted next to each other or on adjacent packaging substrates. A method to fabricate such structures comprises using a template assembly which enables wafer format processing of vertical slice stacks.
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8.发明申请公开(公告)号：US20120307444A1
公开(公告)日：2012-12-06
申请号：US13586054
申请日：2012-08-15
申请人： Evan G. Colgan , Sampath Purushothaman , Roy R. Yu
发明人： Evan G. Colgan , Sampath Purushothaman , Roy R. Yu
CPC分类号： H01L23/49816 , B23P11/00 , H01L21/78 , H01L2924/0002 , H05K1/11 , H05K1/14 , H05K7/00 , Y10T29/49826 , H01L2924/00
摘要： An enhanced 3D integration structure comprises a logic microprocessor chip bonded to a collection of vertically stacked memory slices and an optional set of outer vertical slices comprising optoelectronic devices. Such a device enables both high memory content in close proximity to the logic circuits and a high bandwidth for logic to memory communication. Additionally, the provision of optoelectronic devices in the outer slices of the vertical slice stack enables high bandwidth direct communication between logic processor chips on adjacent enhanced 3D modules mounted next to each other or on adjacent packaging substrates. A method to fabricate such structures comprises using a template assembly which enables wafer format processing of vertical slice stacks.
摘要翻译： 增强的3D集成结构包括结合到垂直堆叠的存储器片的集合的逻辑微处理器芯片和包括光电子器件的可选的一组外部垂直片。 这样一种装置使得能够靠近逻辑电路的高存储器内容和用于逻辑到存储器通信的高带宽。 此外，在垂直切片堆叠的外切片中提供光电子器件可实现彼此相邻或相邻封装衬底上安装的相邻增强型3D模块之间的逻辑处理器芯片之间的高带宽直接通信。 制造这种结构的方法包括使用能够对垂直切片堆叠进行晶片格式处理的模板组件。
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9.发明申请COMPUTER READABLE MEDIUM ENCODED WITH A PROGRAM FOR FABRICATING 3D INTEGRATED CIRCUIT DEVICE USING INTERFACE WAFER AS PERMANENT CARRIER 有权使用接口作为永久载体制作3D集成电路设备的程序编写的计算机可读介质公开(公告)号：US20150024548A1
公开(公告)日：2015-01-22
申请号：US13572004
申请日：2012-08-10
申请人： Mukta G. Farooq , Robert Hannon , Subramanian S. Iyer , Steven J. Koester , Fei Liu , Sampath Purushothaman , Albert M. Young , Roy R. Yu
发明人： Mukta G. Farooq , Robert Hannon , Subramanian S. Iyer , Steven J. Koester , Fei Liu , Sampath Purushothaman , Albert M. Young , Roy R. Yu
IPC分类号： H01L25/065 , H01L25/00
CPC分类号： H01L25/0657 , H01L21/6835 , H01L25/18 , H01L25/50 , H01L2221/68377 , H01L2224/0401 , H01L2224/05001 , H01L2224/05008 , H01L2224/05009 , H01L2224/05024 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05558 , H01L2224/05568 , H01L2224/0557 , H01L2224/056 , H01L2224/131 , H01L2224/16227 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/33181 , H01L2224/73153 , H01L2224/73253 , H01L2224/83121 , H01L2224/83895 , H01L2224/92242 , H01L2224/94 , H01L2225/06513 , H01L2225/06541 , H01L2225/06593 , H01L2924/10253 , H01L2924/14 , H01L2924/1431 , H01L2924/1433 , H01L2924/1434 , H01L2924/1436 , H01L2924/1437 , H01L2924/15311 , H01L2924/157 , H01L2924/37001 , H01L2224/83 , H01L2224/11 , H01L2924/014 , H01L2924/00014
摘要： A computer readable medium is provided that is encoded with a program comprising instructions for performing a method for fabricating a 3D integrated circuit structure. Provided are an interface wafer including a first wiring layer and through-silicon vias, and a first active circuitry layer wafer including active circuitry. The first active circuitry layer wafer is bonded to the interface wafer. Then, a first portion of the first active circuitry layer wafer is removed such that a second portion remains attached to the interface wafer. A stack structure including the interface wafer and the second portion of the first active circuitry layer wafer is bonded to a base wafer. Next, the interface wafer is thinned so as to form an interface layer, and metallizations coupled through the through-silicon vias in the interface layer to the first wiring layer are formed on the interface layer.
摘要翻译： 提供了一种计算机可读介质，其由包含用于执行制造3D集成电路结构的方法的指令的程序编码。 提供了包括第一布线层和穿硅通孔的接口晶片，以及包括有源电路的第一有源电路层晶片。 第一有源电路层晶片被结合到界面晶片。 然后，去除第一有源电路层晶片的第一部分，使得第二部分保持附着到界面晶片。 包括接口晶片和第一有源电路层晶片的第二部分的堆叠结构被结合到基底晶片。 接下来，将界面晶片减薄以形成界面层，并且在界面层上形成通过界面层中的穿硅通孔耦合到第一布线层的金属化。
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10.发明授权3D integrated circuit device fabrication with precisely controllable substrate removal 有权3D集成电路器件制造具有精确可控的衬底去除公开(公告)号：US08738167B2
公开(公告)日：2014-05-27
申请号：US13398481
申请日：2012-02-16
申请人： Mukta G. Farooq , Robert Hannon , Subramanian S. Iyer , Steven J. Koester , Sampath Purushothaman , Roy R. Yu
发明人： Mukta G. Farooq , Robert Hannon , Subramanian S. Iyer , Steven J. Koester , Sampath Purushothaman , Roy R. Yu
CPC分类号： H01L27/105 , H01L24/11 , H01L27/0688 , H01L2224/05008 , H01L2224/05009 , H01L2224/05024 , H01L2224/05147 , H01L2224/05184 , H01L2224/05568 , H01L2224/0557 , H01L2924/00014 , H01L2924/14 , H01L2924/00 , H01L2224/05599
摘要： A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer is provided. The first active circuitry layer wafer comprises a P+ portion covered by a P− layer, and the P− layer includes active circuitry. The first active circuitry layer wafer is bonded face down to an interface wafer that includes a first wiring layer, and then the P+ portion of the first active circuitry layer wafer is selectively removed with respect to the P− layer of the first active circuitry layer wafer. Next, a wiring layer is fabricated on the backside of the P− layer. Also provided are a non-transitory computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, and a 3D integrated circuit structure.
摘要翻译： 提供了一种用于制造3D集成电路结构的方法。 根据该方法，提供第一有源电路层晶片。 第一有源电路层晶片包括由P层覆盖的P +部分，并且P层包括有源电路。 第一有源电路层晶片面向下接合到包括第一布线层的接口晶片，然后相对于第一有源电路层晶片的P层选择性地去除第一有源电路层晶片的P +部分 。 接下来，在P-层的背面上制造布线层。 还提供了编码有用于制造3D集成电路结构的程序的非暂时计算机可读介质，以及3D集成电路结构。
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