公开(公告)号：US09728583B2

公开(公告)日：2017-08-08

申请号：US15249559

申请日：2016-08-29

Applicant: Everspin Technologies, Inc.

Inventor： Kerry Joseph Nagel ,  Sanjeev Aggarwal ,  Moazzem Hossain ,  Nicholas Rizzo

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12 ,  G11C11/16 ,  H01L43/08

CPC classification number: H01L27/222 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: A layer of silicon nitride above the bottom electrode and on the sidewalls of the magnetoresistive stack serves as an insulator and an etch stop during manufacturing of a magnetoresistive device. Non-selective chemical mechanical polishing removes any silicon nitride overlying a top electrode for the device along with silicon dioxide used for encapsulation. Later etching operations corresponding to formation of a via to reach the top electrode use selective etching chemistries that remove silicon dioxide to access the top electrode, but do not remove silicon nitride. Thus, the silicon nitride acts as an etch stop, and, in the resulting device, provides an insulating layer that prevents unwanted short circuits between the via and the bottom electrode and between the via and the sidewalls of the magnetoresistive device stack.

公开(公告)号：US20150236254A1

公开(公告)日：2015-08-20

申请号：US14704915

申请日：2015-05-05

Applicant: Everspin Technologies, Inc.

Inventor： Kerry Joseph Nagel ,  Kenneth Smith ,  Moazzem Hossain ,  Sanjeev Aggarwal

IPC: H01L43/12 ,  H01L43/08 ,  H01L21/285 ,  H01L21/768 ,  H01L21/3213 ,  H01L43/02 ,  H01L27/22

CPC classification number: H01L43/12 ,  H01L21/28568 ,  H01L21/32133 ,  H01L21/76819 ,  H01L21/7684 ,  H01L21/76877 ,  H01L27/222 ,  H01L27/226 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08

Abstract: A conductive via disposed beneath a magnetic device and aligned therewith. In certain embodiments, an electrode formed on the conductive via may be polished to eliminate step functions or seams originating at the conductive via from propagating up through the various deposited layers. This integration approach allows for improved scaling of the MRAM devices to, for example, a 45 nanometer node.

Abstract translation: 导电通孔，其设置在磁性装置的下方并与其对准。 在某些实施例中，形成在导电通孔上的电极可以被抛光以消除起始于导电通孔的步骤功能或接缝，以向上传播通过各种沉积层。 该集成方法允许将MRAM设备改进为例如45纳米节点。

公开(公告)号：US11031546B2

公开(公告)日：2021-06-08

申请号：US16194523

申请日：2018-11-19

Applicant: Everspin Technologies, Inc.

Inventor： Kerry Joseph Nagel ,  Kenneth H. Smith ,  Moazzem Hossain ,  Sanjeev Aggarwal

IPC: H01L21/3213 ,  H01L27/22 ,  H01L43/12 ,  H01L43/08 ,  H01L21/768 ,  H01L21/285 ,  H01L43/02

Abstract: A method of manufacturing one or more interconnects to magnetoresistive structure comprising (i) depositing a first conductive material in a via; (2) etching the first conductive material wherein, after etching the first conductive material a portion of the first conductive material remains in the via, (3) partially filling the via by depositing a second conductive material in the via and directly on the first conductive material in the via; (4) depositing a first electrode material in the via and directly on the second conductive material in the via; (5) polishing a first surface of the first electrode material wherein, after polishing, the first electrode material is (i) on the second conductive material in the via and (ii) over the portion of the first conductive material remaining in the via; and (6) forming a magnetoresistive structure over the first electrode material.

公开(公告)号：US10297747B2

公开(公告)日：2019-05-21

申请号：US15958444

申请日：2018-04-20

Applicant: Everspin Technologies, Inc.

Inventor： Sarin A. Deshpande ,  Sanjeev Aggarwal ,  Moazzem Hossain

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01L21/768

Abstract: The present disclosure is drawn to, among other things, a method of fabricating an integrated circuit device having a magnetoresistive device. In some aspects, the method includes forming the magnetoresistive device on a first contact of a substrate, wherein the magnetoresistive device includes a fixed magnetic region and a free magnetic region separated by an intermediate region; depositing a first dielectric material over the magnetoresistive device; depositing a second dielectric material over the first dielectric material; polishing a surface of the second dielectric material; forming a first cavity through the polished surface of the second dielectric material to expose a surface of the magnetoresistive device; and depositing an electrically conductive material in the first cavity to form a via.

公开(公告)号：US09431602B2

公开(公告)日：2016-08-30

申请号：US14297389

申请日：2014-06-05

Applicant: Everspin Technologies, Inc.

Inventor： Kerry Joseph Nagel ,  Sanjeev Aggarwal ,  Moazzem Hossain ,  Nicholas Rizzo

IPC: H01L43/12

CPC classification number: H01L27/222 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: A layer of silicon nitride above the bottom electrode and on the sidewalls of the magnetoresistive stack serves as an insulator and an etch stop during manufacturing of a magnetoresistive device. Non-selective chemical mechanical polishing removes any silicon nitride overlying a top electrode for the device along with silicon dioxide used for encapsulation. Later etching operations corresponding to formation of a via to reach the top electrode use selective etching chemistries that remove silicon dioxide to access the top electrode, but do not remove silicon nitride. Thus, the silicon nitride acts as an etch stop, and, in the resulting device, provides an insulating layer that prevents unwanted short circuits between the via and the bottom electrode and between the via and the sidewalls of the magnetoresistive device stack.

Abstract translation: 在磁阻堆叠的底部电极和侧壁上方的氮化硅层用作磁阻器件的制造期间的绝缘体和蚀刻停止。 非选择性化学机械抛光除了用于器件的顶部电极以及用于封装的二氧化硅之外的任何氮化硅。 对应于形成通孔以到达顶部电极的后来的蚀刻操作使用去除二氧化硅以进入顶部电极但是不去除氮化硅的选择性蚀刻化学品。 因此，氮化硅用作蚀刻停止，并且在所得到的器件中提供了防止通孔和底部电极之间以及磁阻器件堆叠的通路和侧壁之间的不期望的短路的绝缘层。

公开(公告)号：US11631806B2

公开(公告)日：2023-04-18

申请号：US17317061

申请日：2021-05-11

Applicant: Everspin Technologies, Inc.

Inventor： Kerry Joseph Nagel ,  Kenneth Smith ,  Moazzem Hossain ,  Sanjeev Aggarwal

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/08 ,  H01L21/768 ,  H01L21/285 ,  H01L21/3213 ,  H01L43/02

Abstract: A method of manufacturing one or more interconnects to magnetoresistive structure comprising (i) depositing a first conductive material in a via; (2) etching the first conductive material wherein, after etching the first conductive material a portion of the first conductive material remains in the via, (3) partially filling the via by depositing a second conductive material in the via and directly on the first conductive material in the via; (4) depositing a first electrode material in the via and directly on the second conductive material in the via; (5) polishing a first surface of the first electrode material wherein, after polishing, the first electrode material is (i) on the second conductive material in the via and (ii) over the portion of the first conductive material remaining in the via; and (6) forming a magnetoresistive structure over the first electrode material.

公开(公告)号：US08877522B2

公开(公告)日：2014-11-04

申请号：US14283413

申请日：2014-05-21

Applicant: EverSpin Technologies, Inc.

Inventor： Kerry Nagel ,  Sarin Deshpande ,  Moazzem Hossain ,  Sanjeev Aggarwal

IPC: H01L21/00 ,  G11C11/00 ,  H01L43/12 ,  H01L21/768 ,  H01L27/22

CPC classification number: H01L43/12 ,  H01L21/76883 ,  H01L21/76898 ,  H01L23/544 ,  H01L27/222 ,  H01L2223/54426 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method is provided for forming a first via with an electrically conductive material, for example, copper, that is formed over and coupled to a conductive landing pad of an MRAM array. A sputter step is performed to lower the surface of the first via below that of a surrounding dielectric material. This recess is repeated in subsequent processing steps, providing alignment marks for the formation of a magnetic tunnel junction. The magnetic tunnel junction may be offset from the first via, and a second via being formed above the magnetic tunnel junction and to a conductive layer.

Abstract translation: 提供了一种用于形成第一通孔的方法，其中导电材料例如铜形成在MRAM阵列的导电着陆焊盘上并耦合到MRAM阵列的导电着陆焊盘。 执行溅射步骤以将第一通孔的表面降低到低于周围电介质材料的表面。 在随后的处理步骤中重复该凹槽，提供用于形成磁性隧道结的对准标记。 磁性隧道结可以偏离第一通孔，并且第二通孔形成在磁性隧道结上方和导电层上。

公开(公告)号：US20150357559A1

公开(公告)日：2015-12-10

申请号：US14297389

申请日：2014-06-05

Applicant: Everspin Technologies, Inc.

Inventor： Kerry Joseph Nagel ,  Sanjeev Aggarwal ,  Moazzem Hossain ,  Nicholas Rizzo

IPC: H01L43/08 ,  H01L43/12 ,  H01L45/00 ,  H01L43/02

CPC classification number: H01L27/222 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: A layer of silicon nitride above the bottom electrode and on the sidewalls of the magnetoresistive stack serves as an insulator and an etch stop during manufacturing of a magnetoresistive device. Non-selective chemical mechanical polishing removes any silicon nitride overlying a top electrode for the device along with silicon dioxide used for encapsulation. Later etching operations corresponding to formation of a via to reach the top electrode use selective etching chemistries that remove silicon dioxide to access the top electrode, but do not remove silicon nitride. Thus, the silicon nitride acts as an etch stop, and, in the resulting device, provides an insulating layer that prevents unwanted short circuits between the via and the bottom electrode and between the via and the sidewalls of the magnetoresistive device stack.

Abstract translation: 在磁阻堆叠的底部电极和侧壁上方的氮化硅层用作磁阻器件的制造期间的绝缘体和蚀刻停止。 非选择性化学机械抛光除了用于器件的顶部电极以及用于封装的二氧化硅之外的任何氮化硅。 对应于形成通孔以到达顶部电极的后来的蚀刻操作使用去除二氧化硅以进入顶部电极但是不去除氮化硅的选择性蚀刻化学品。 因此，氮化硅用作蚀刻停止，并且在所得到的器件中提供了防止通孔和底部电极之间以及磁阻器件堆叠的通路和侧壁之间的不期望的短路的绝缘层。

公开(公告)号：US10541362B2

公开(公告)日：2020-01-21

申请号：US16380589

申请日：2019-04-10

Applicant: Everspin Technologies, Inc.

Inventor： Sarin A. Deshpande ,  Sanjeev Aggarwal ,  Moazzem Hossain

IPC: H01L27/22 ,  H01L21/768 ,  H01L43/12 ,  H01L43/02 ,  G11C11/16 ,  H01L43/08

Abstract: The present disclosure is drawn to, among other things, a method of fabricating an integrated circuit device having a magnetoresistive device. In some aspects, the method includes forming the magnetoresistive device on a first contact of a substrate, wherein the magnetoresistive device includes a fixed magnetic region and a free magnetic region separated by an intermediate region; depositing a first dielectric material over the magnetoresistive device; depositing a second dielectric material over the first dielectric material; polishing a surface of the second dielectric material; forming a first cavity through the polished surface of the second dielectric material to expose a surface of the magnetoresistive device; and depositing an electrically conductive material in the first cavity to form a via.

公开(公告)号：US10164176B2

公开(公告)日：2018-12-25

申请号：US15399971

申请日：2017-01-06

Applicant: Everspin Technologies, Inc.

Inventor： Kerry Joseph Nagel ,  Kenneth Smith ,  Moazzem Hossain ,  Sanjeev Aggarwal

IPC: H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01L27/22 ,  H01L21/285 ,  H01L21/3213 ,  H01L21/768

Abstract: A method of manufacturing one or more interconnects to a magnetoresistive structure, the method comprising depositing a first conductive material (i) in a via which is formed through a first surface of a first dielectric layer and (ii) directly on the first surface of the first dielectric layer. The method further includes etching the first conductive material wherein, after etching the first conductive material, a portion of the first conductive material remains (i) in the via and (ii) directly on the first surface of the first dielectric layer. The method also includes partially filling the via by depositing a second conductive material (i) in the via and (ii) directly on the first conductive material remaining in the via, depositing a first electrode material (i) in the via and (ii) directly on the second conductive material which is in the via, and forming a magnetoresistive structure over the first electrode material.