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    Split-gate non-volatile memory (NVM) cell and method therefor
    1.
    发明授权
    Split-gate non-volatile memory (NVM) cell and method therefor 有权

    公开(公告)号：US09728410B2

    公开(公告)日：2017-08-08

    申请号：US14508629

    申请日：2014-10-07

    Applicant: FREESCALE SEMICONDUCTOR, INC.

    Inventor： Craig T. Swift ,  Asanga H. Perera

    IPC: H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792 ,  H01L29/788

    CPC classification number: H01L21/28273 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881

    Abstract: A split gate memory device includes a semiconductor substrate and a select gate over the substrate. The select gate has a bottom portion and a top portion over the bottom portion, wherein the top portion has a top sidewall and the bottom portion has a bottom sidewall, and wherein the bottom sidewall extends beyond the top sidewall. The devices also includes a control gate adjacent the select gate, a charge storage layer located between the select gate and the control gate and between the control gate and the substrate, and an isolation region over the bottom portion of the select gate and between the top sidewall of the select gate and the charge storage layer. The bottom sidewall of the bottom portion extends to the charge storage layer.

    Low Resistance Polysilicon Strap
    2.
    发明申请
    Low Resistance Polysilicon Strap 有权
    低电阻多晶硅带

    公开(公告)号：US20160087057A1

    公开(公告)日：2016-03-24

    申请号：US14960211

    申请日：2015-12-04

    Applicant: Freescale Semiconductor Inc.

    Inventor： Anirban Roy ,  Craig T. Swift

    IPC: H01L29/423 ,  H01L29/40 ,  H01L29/792

    CPC classification number: H01L29/42344 ,  G11C16/0425 ,  H01L21/28273 ,  H01L29/408 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7883 ,  H01L29/7885 ,  H01L29/792

    Abstract: A low resistance polysilicon (poly) structure includes a first poly coupled to a substrate and having a sidewall. A second poly is separated from the sidewall of the first poly and the substrate by a programming oxide. The first poly and the second poly have substantially a same planarized height above the substrate. The first poly extends from a device region to a strap region, and extends substantially parallel to a first length of the second poly. A second length of the second poly extends away from the first poly in the strap region and includes a salicide. A first diffusion region crosses the first poly and the second poly in the device region. A masked width of the first length of the second poly is defined by an etched spacer. A low resistance contact is coupled to the second length of the second poly in the strap region.

    Abstract translation: 低电阻多晶硅（poly）结构包括耦合到衬底并具有侧壁的第一聚酯。 第二聚合物通过编程氧化物与第一多晶硅和衬底的侧壁分离。 第一聚合物和第二聚合物在基材上方具有基本相同的平坦化高度。 第一聚氨酯从器件区域延伸到带区域，并且基本上平行于第二聚合物的第一长度延伸。 第二聚合物的第二长度在带区域中远离第一聚合物延伸并且包括自对准硅化物。 第一扩散区域在器件区域中与第一聚合物和第二聚合物交叉。 第二聚合物的第一长度的掩蔽宽度由蚀刻间隔物限定。 低电阻触点在带区域中耦合到第二聚合物的第二长度。

    Low resistance polysilicon strap
    3.
    发明授权
    Low resistance polysilicon strap 有权
    低电阻多晶硅带

    公开(公告)号：US09236498B1

    公开(公告)日：2016-01-12

    申请号：US14470894

    申请日：2014-08-27

    Applicant: Freescale Semiconductor Inc.

    Inventor： Anirban Roy ,  Craig T. Swift

    IPC: H01L27/115 ,  H01L29/792 ,  H01L29/66

    CPC classification number: H01L29/42344 ,  G11C16/0425 ,  H01L21/28273 ,  H01L29/408 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7883 ,  H01L29/7885 ,  H01L29/792

    Abstract: A low resistance polysilicon (poly) structure includes a first poly coupled to a substrate and having a sidewall. A second poly is separated from the sidewall of the first poly and the substrate by a programming oxide. The first poly and the second poly have substantially a same planarized height above the substrate. The first poly extends from a device region to a strap region, and extends substantially parallel to a first length of the second poly. A second length of the second poly extends away from the first poly in the strap region and includes a salicide. A first diffusion region crosses the first poly and the second poly in the device region. A masked width of the first length of the second poly is defined by an etched spacer. A low resistance contact is coupled to the second length of the second poly in the strap region.

    Abstract translation: 低电阻多晶硅（poly）结构包括耦合到衬底并具有侧壁的第一聚酯。 第二聚合物通过编程氧化物与第一多晶硅和衬底的侧壁分离。 第一聚合物和第二聚合物在基材上方具有基本相同的平坦化高度。 第一聚氨酯从器件区域延伸到带区域，并且基本上平行于第二聚合物的第一长度延伸。 第二聚合物的第二长度在带区域中远离第一聚合物延伸并且包括自对准硅化物。 第一扩散区域在器件区域中与第一聚合物和第二聚合物交叉。 第二聚合物的第一长度的掩蔽宽度由蚀刻间隔物限定。 低电阻触点在带区域中耦合到第二聚合物的第二长度。

    Embedded data and code non-volatile memory cell configurations
    5.
    发明授权
    Embedded data and code non-volatile memory cell configurations 有权
    嵌入式数据和代码非易失性存储单元配置

    公开(公告)号：US09293207B1

    公开(公告)日：2016-03-22

    申请号：US14612907

    申请日：2015-02-03

    Applicant: FREESCALE SEMICONDUCTOR, INC.

    Inventor： Craig T. Swift

    IPC: G11C16/04 ,  G11C16/14

    CPC classification number: G11C11/005 ,  G11C16/0425 ,  G11C16/0466 ,  G11C16/3495 ,  G11C2216/06

    Abstract: An integrated circuit including data and code non-volatile memory configuration is provided. The integrated circuit comprises a first non-volatile memory array for storing code and a second non-volatile memory array for storing data. The first non-volatile memory array comprises a plurality of first non-volatile memory cells, the first non-volatile memory cells each having a first channel width. The second non-volatile memory array comprises a plurality of second non-volatile memory cells, the second non-volatile memory cells each having a second channel width. The second channel width of the second non-volatile memory cells is larger than the first channel width of the first non-volatile memory cells. This allows the data non-volatile memory cells to have a higher transconductance than the code non-volatile memory cells.

    Abstract translation: 提供了包括数据和代码非易失性存储器配置的集成电路。 集成电路包括用于存储代码的第一非易失性存储器阵列和用于存储数据的第二非易失性存储器阵列。 第一非易失性存储器阵列包括多个第一非易失性存储器单元，每个第一非易失性存储单元具有第一通道宽度。 第二非易失性存储器阵列包括多个第二非易失性存储器单元，每个第二非易失性存储单元具有第二通道宽度。 第二非易失性存储单元的第二通道宽度大于第一非易失性存储单元的第一通道宽度。 这允许数据非易失性存储单元具有比代码非易失性存储单元更高的跨导。

    Non-volatile memory (NVM) with endurance control
    6.
    发明授权
    Non-volatile memory (NVM) with endurance control 有权
    具有耐久性控制的非易失性存储器（NVM）

    公开(公告)号：US09508397B1

    公开(公告)日：2016-11-29

    申请号：US14957778

    申请日：2015-12-03

    Applicant: FREESCALE SEMICONDUCTOR, INC.

    Inventor： Richard K. Eguchi ,  Thomas Jew ,  Craig T. Swift

    IPC: G11C16/10 ,  G11C5/14 ,  G11C7/06

    CPC classification number: G11C16/10 ,  G11C16/08 ,  G11C16/28 ,  G11C16/349 ,  G11C29/021 ,  G11C29/028 ,  G11C29/50004 ,  G11C2029/0409

    Abstract: An operating voltage and reference current are adjusted in a memory device. At least a portion of an array of memory cells is preconditioned to an erased state using an erase verify voltage on word lines coupled to the memory cells and a first reference current in sense amplifiers coupled to bit lines for the array. A test reference current is set for the sense amplifiers. A bitcell gate voltage is set on the word lines to a present overdrive voltage. The at least a portion of the array is read. If any of the memory cells in the at least a portion of the array are read as being programmed, the present overdrive voltage is increased until none of the memory cells in the at least a portion of the array are read as being programmed.

    Abstract translation: 在存储器件中调节工作电压和参考电流。 使用耦合到存储器单元的字线上的擦除验证电压和耦合到阵列的位线的读出放大器中的第一参考电流，将存储器单元阵列的至少一部分预处理为擦除状态。 为读出放大器设置测试参考电流。 字元栅极电压在字线上设置为当前的过驱动电压。 读取阵列的至少一部分。 如果阵列的至少一部分中的任何存储器单元被读取为被编程，则增加当前的过驱动电压，直到阵列的至少一部分中的存储单元都不被读取为被编程为止。

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