公开(公告)号：US09755888B2

公开(公告)日：2017-09-05

申请号：US14884142

申请日：2015-10-15

申请人： FUJITSU LIMITED

发明人： Tomohiro Inoue ,  Shun Ando ,  Shinya Hiramoto ,  Masahiro Maeda ,  Masao Yoshikawa

IPC分类号： H04L12/24 ,  H04L12/931 ,  H04L12/801 ,  H04L1/16 ,  H04L1/20 ,  H04L5/00 ,  H04L1/08

CPC分类号： H04L41/0672 ,  H04L1/08 ,  H04L1/16 ,  H04L1/20 ,  H04L5/0044 ,  H04L47/13 ,  H04L49/352

摘要： An information processing device includes a transfer unit and an interface unit, the interface unit distributes transmission to a plurality of first lanes, and generate reception information from a plurality of pieces of distribution reception data received through a plurality of second lanes, the transfer unit includes a reception processing unit to extract reception data included in the reception information, and first error information indicating an error in any of the first lanes and a degeneration management unit to generate first degeneration information indicating a use stop lane among the first lanes, based on the first error information, generate second degeneration information indicating a use stop lane among the plurality of second lanes, based on second error information that is output from the interface unit, and cause the transmission processing unit to generate transmission information including the second degeneration information.

公开(公告)号：US20160112312A1

公开(公告)日：2016-04-21

申请号：US14875994

申请日：2015-10-06

申请人： FUJITSU LIMITED

发明人： Shinya HIRAMOTO ,  Tomohiro Inoue ,  Shun Ando ,  Masahiro Maeda ,  Masao Yoshikawa

IPC分类号： H04L12/741 ,  H04L12/861

CPC分类号： H04L45/74 ,  H04L49/9005

摘要： A communication apparatus includes a connection port and a processor. The connection port is connected to a switch apparatus. The processor is configured to acquire data to be transmitted to an external apparatus. The processor is configured to generate a packet destined to the external apparatus. The packet contains the data. The processor is configured to store the packet in a buffer. The processor is configured to acquire the packet from the buffer. The processor is configured to transmit the packet to the switch apparatus via the connection port. The processor is configured to acquire a state of a network to which the connection port is connected. The processor is configured to control, on basis of the state of the network and a predetermined packet generation time, a number of packets to be generated.

摘要翻译： 通信装置包括连接端口和处理器。 连接端口连接到开关装置。 处理器被配置为获取要发送到外部设备的数据。 处理器被配置为生成去往外部设备的分组。 数据包包含数据。 处理器被配置为将数据包存储在缓冲器中。 处理器被配置为从缓冲器获取分组。 处理器被配置为经由连接端口将数据包发送到交换设备。 处理器被配置为获取连接端口连接到的网络的状态。 处理器被配置为基于网络的状态和预定的分组生成时间来控制要生成的分组的数量。

公开(公告)号：US09893992B2

公开(公告)日：2018-02-13

申请号：US14875994

申请日：2015-10-06

申请人： FUJITSU LIMITED

发明人： Shinya Hiramoto ,  Tomohiro Inoue ,  Shun Ando ,  Masahiro Maeda ,  Masao Yoshikawa

IPC分类号： H04L12/26 ,  H04L12/741 ,  H04L12/861

CPC分类号： H04L45/74 ,  H04L49/9005

摘要： A communication apparatus includes a connection port and a processor. The connection port is connected to a switch apparatus. The processor is configured to acquire data to be transmitted to an external apparatus. The processor is configured to generate a packet destined to the external apparatus. The packet contains the data. The processor is configured to store the packet in a buffer. The processor is configured to acquire the packet from the buffer. The processor is configured to transmit the packet to the switch apparatus via the connection port. The processor is configured to acquire a state of a network to which the connection port is connected. The processor is configured to control, on basis of the state of the network and a predetermined packet generation time, a number of packets to be generated.