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    PROCESSOR AND INFORMATION PROCESSING APPARATUS
    1.
    发明申请
    PROCESSOR AND INFORMATION PROCESSING APPARATUS 审中-公开

    公开(公告)号：US20200028729A1

    公开(公告)日：2020-01-23

    申请号：US16439788

    申请日：2019-06-13

    申请人： FUJITSU LIMITED

    发明人： Makoto SUGA ,  Shun Ando

    IPC分类号： H04L12/24

    摘要： A processor includes a controller that measures an error rate of a signal that propagates through a communication line; switches to use a spare line to perform a first communication when a first error rate of a signal that propagates through a first communication line of a first line group exceeds a first threshold, the first communication being performed using the first communication line; and switches to use the first communication line to perform the first communication and switches to use the spare line to perform a second communication when the first communication is performed using the spare line, when a second error rate of a signal that propagates through a second communication line of a second line group exceeds a second threshold higher than the first threshold, and when the first error rate is lower than the second threshold; and a processor core that exchanges information via the controller.

    Parallel computer system, control method of parallel computer system, information processing device, arithmetic processing device, and communication control device
    2.
    发明授权
    Parallel computer system, control method of parallel computer system, information processing device, arithmetic processing device, and communication control device 有权
    并行计算机系统，并行计算机系统的控制方法，信息处理装置，算术处理装置和通信控制装置

    公开(公告)号：US09542313B2

    公开(公告)日：2017-01-10

    申请号：US14540381

    申请日：2014-11-13

    申请人： FUJITSU LIMITED

    发明人： Shinya Hiramoto ,  Tomohiro Inoue ,  Masahiro Maeda ,  Shun Ando ,  Yuta Toyoda

    IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/08 ,  G06F9/52

    CPC分类号： G06F12/0804 ,  G06F9/526 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0842 ,  G06F2212/1024 ,  G06F2212/283

    摘要： A parallel computer system includes information processing devices, each of the information processing devices including a communication control device that performs communication, a main memory that stores data, and an arithmetic processing device that is coupled to the communication control device and the main memory, the information processing devices being coupled to each other through a network by the respective communication control device, wherein the arithmetic processing device includes a cache memory and a cache controller, the cache controller that executes an atomic operation for target data on the cache memory that stores the target data when the communication control device outputs an atomic operation request that is used to request the atomic operation, the atomic operation being not divided into a smaller operation, and notifies the communication control device of a result that is obtained by executing the atomic operation on the cache memory.

    摘要翻译： 并行计算机系统包括信息处理设备，每个信息处理设备包括执行通信的通信控制设备，存储数据的主存储器和耦合到通信控制设备和主存储器的算术处理设备， 信息处理设备通过相应的通信控制设备通过网络彼此耦合，其中所述算术处理设备包括高速缓存存储器和高速缓存控制器，所述高速缓存控制器对存储所述高速缓冲存储器的高速缓冲存储器上的目标数据执行原子操作 当通信控制装置输出用于请求原子操作的原子操作请求时，原子操作不被划分为更小的操作，并将通过执行原子操作获得的结果通知给通信控制装置， 缓存内存。

    Parallel computer system, data transfer device, and method for controlling parallel computer system for performing arbitration
    5.
    发明授权
    Parallel computer system, data transfer device, and method for controlling parallel computer system for performing arbitration 有权
    并行计算机系统，数据传输设备和并行计算机系统执行仲裁的方法

    公开(公告)号：US09336172B2

    公开(公告)日：2016-05-10

    申请号：US13920750

    申请日：2013-06-18

    申请人： FUJITSU LIMITED

    发明人： Shun Ando ,  Shinya Hiramoto ,  Tomohiro Inoue ,  Yuta Toyoda ,  Masahiro Maeda ,  Yuichiro Ajima

    IPC分类号： G06F13/36 ,  G06F13/40

    CPC分类号： G06F13/4022 ,  G06F13/4027

    摘要： A switch includes a plurality of ports and a combination determining unit that determines a central processing unit (CPU) to be paired with one of the ports. The port includes: an arbitration circuit that selects the CPU to be paired therewith when receiving an arbitration request from the CPU to be paired in a predetermined state, and selects one of the CPUs from which the arbitration request has been received in other cases to return transmission permission; and a data transfer unit that transfers the received data from the selected CPU to another CPU. The CPU includes: a request transmission unit that transmits the arbitration request to the ports; and a data transmission unit that transmits data to the paired port when the arbitration request is transmitted to the paired port in the predetermined state, and transmits data to the ports that have returned transmission permission in other cases.

    摘要翻译： 开关包括多个端口和组合确定单元，其确定要与其中一个端口配对的中央处理单元（CPU）。 该端口包括：仲裁电路，当从预定状态的CPU中接收到仲裁请求时，选择要配对的CPU，并且在其他情况下选择其中接收到仲裁请求的一个CPU返回 传输许可; 以及将所接收的数据从所选择的CPU传送到另一个CPU的数据传送单元。 CPU包括：向该端口发送仲裁请求的请求发送单元; 以及数据传输单元，当在预定状态下将仲裁请求发送到配对端口时，将数据发送到配对端口，并且在其他情况下向发送许可的端口发送数据。

    PARALLEL COMPUTER SYSTEM, DATA TRANSFER DEVICE, AND METHOD FOR CONTROLLING PARALLEL COMPUTER SYSTEM
    6.
    发明申请
    PARALLEL COMPUTER SYSTEM, DATA TRANSFER DEVICE, AND METHOD FOR CONTROLLING PARALLEL COMPUTER SYSTEM 有权
    并行计算机系统，数据传输设备和控制并行计算机系统的方法

    公开(公告)号：US20140052885A1

    公开(公告)日：2014-02-20

    申请号：US13920750

    申请日：2013-06-18

    申请人： FUJITSU LIMITED

    发明人： Shun Ando ,  Shinya Hiramoto ,  Tomohiro Inoue ,  Yuta Toyoda ,  Masahiro Maeda ,  Yuichiro Ajima

    IPC分类号： G06F13/40

    CPC分类号： G06F13/4022 ,  G06F13/4027

    摘要： A switch includes a plurality of ports and a combination determining unit that determines a central processing unit (CPU) to be paired with one of the ports. The port includes: an arbitration circuit that selects the CPU to be paired therewith when receiving an arbitration request from the CPU to be paired in a predetermined state, and selects one of the CPUs from which the arbitration request has been received in other cases to return transmission permission; and a data transfer unit that transfers the received data from the selected CPU to another CPU. The CPU includes: a request transmission unit that transmits the arbitration request to the ports; and a data transmission unit that transmits data to the paired port when the arbitration request is transmitted to the paired port in the predetermined state, and transmits data to the ports that have returned transmission permission in other cases.

    摘要翻译： 开关包括多个端口和组合确定单元，其确定要与其中一个端口配对的中央处理单元（CPU）。 该端口包括：仲裁电路，当从预定状态的CPU中接收到仲裁请求时，选择要配对的CPU，并且在其他情况下选择其中接收到仲裁请求的一个CPU返回 传输许可; 以及将所接收的数据从所选择的CPU传送到另一个CPU的数据传送单元。 CPU包括：向该端口发送仲裁请求的请求发送单元; 以及数据传输单元，当在预定状态下将仲裁请求发送到配对端口时，将数据发送到配对端口，并且在其他情况下向发送许可的端口发送数据。

    Storage control apparatus, method of setting reference time, and computer-readable storage medium storing reference time setting program
    8.
    发明授权
    Storage control apparatus, method of setting reference time, and computer-readable storage medium storing reference time setting program 有权
    存储控制装置，设定基准时间的方法以及存储基准时间设定程序的计算机可读存储介质

    公开(公告)号：US09152519B2

    公开(公告)日：2015-10-06

    申请号：US13858130

    申请日：2013-04-08

    申请人： FUJITSU LIMITED

    发明人： Shun Ando ,  Yuji Noda

    IPC分类号： G06F11/00 ,  G06F11/26 ,  G06F11/07 ,  G06F3/06

    CPC分类号： G06F11/26 ,  G06F3/0619 ,  G06F3/0676 ,  G06F11/0757

    摘要： With a command delay time measurement unit that issues a first test command while the medium error status generator generates the medium error status, and measures a delay time of a command response for the first test command as a command delay time, and a response interval measurement unit that issues a plurality of second test commands to the storage apparatuses to be examined under a higher load when no error occurs, and measures an interval of each command response for the plurality of second test commands as a response interval, and by calculating, for each of the plurality of types of the storage apparatuses, a reference time for each storage apparatus type by adding the command delay time and the response interval, an error can be detected more efficiently.

    摘要翻译： 利用命令延迟时间测量单元，其在中间错误状态发生器产生介质错误状态时发出第一测试命令，并且测量第一测试命令的命令响应的延迟时间作为命令延迟时间，以及响应间隔测量 在没有发生错误的情况下，向较高负载下检查的存储装置发出多个第二测试命令的单元，并且测量作为响应间隔的多个第二测试命令的每个命令响应的间隔，并且通过计算对于 通过添加命令延迟时间和响应间隔，多种类型的存储装置中的每一种，每种存储装置类型的参考时间可以更有效地检测。

    Storage system, controller module and method of controlling storage system
    9.
    发明授权
    Storage system, controller module and method of controlling storage system 有权
    存储系统，控制器模块和控制存储系统的方法

    公开(公告)号：US09104230B2

    公开(公告)日：2015-08-11

    申请号：US13685963

    申请日：2012-11-27

    申请人： FUJITSU LIMITED

    发明人： Shun Ando

    IPC分类号： G06F13/30 ,  G06F3/00 ,  G06F3/06

    CPC分类号： G06F3/00 ,  G06F3/0611 ,  G06F3/0659 ,  G06F3/0689

    摘要： A storage-system includes a storage-device, a first-device that controls to transfer data to-and-fro the storage-device and a second-device redundant from the first-device, wherein the first-device includes a processing-device that processes a command related to input-and-output of data stored in the storage-device, a storage-unit that stores, in a correlated manner, the number of commands issued collectively during download of firmware for controlling the processing-device and response delay-time representing time in which a response has been delayed due to the download in a correlated manner, and a control-unit which retrieves the number of issuable commands corresponding to acceptable response-delay-time of the command during download and restricts issue of the command for which an issue request has been newly made if the number of commands being issued is equal to or greater than the retrieved number of issuable commands during the download, when a download request is made.

    摘要翻译： 一种存储系统包括一个存储设备，一个第一设备，用于控制来自存储设备的数据的传送和从第一设备冗余的第二设备，其中第一设备包括一个处理设备 处理与存储在存储装置中的数据的输入和输出有关的命令;存储单元，以相关方式存储在下载用于控制处理装置和响应的固件期间共同发出的命令数 延迟时间表示由于以相关方式下载响应已被延迟的时间;以及控制单元，其检索与下载期间的命令的可接受的响应延迟时间相对应的可发出命令的数量，并且限制发布 如果在下载期间发出命令的数量等于或大于检索到的可发布命令的数量，则当进行下载请求时，重新发出发出请求的命令。